Synchronization circuit for a write operation on a...

Details Synchronization circuit for a write operation on a... Synchronization circuit for a write operation on a...

2006-11-06

2008-10-28

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S221000

Reexamination Certificate

active

07443762

ABSTRACT:
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.

REFERENCES:
patent: 5594927 (1997-01-01), Lee et al.
patent: 6337809 (2002-01-01), Kim et al.
HYB18H512321AF-12/14/16/20 “512-Mbit GDDR3 Graphics RAM—RoHS Compliant—Memory Products,”Infineon TechnologiesData Sheet dated Aug. 2005.

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