Synchronization circuit for a synchronous switching system

Details Synchronization circuit for a synchronous switching system Synchronization circuit for a synchronous switching system

1991-02-20

1992-07-28

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

3701051, H04L 700

Patent

active

051346362

ABSTRACT:
The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

REFERENCES:
patent: 4763339 (1988-08-01), Sutphin et al.
patent: 4943985 (1990-07-01), Gherardi
patent: 4984238 (1991-01-01), Watanabe et al.
patent: 5046074 (1991-09-01), Abiven et al.

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