Synchronization circuit configuration

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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378 63, 378 72, H03L 700, H03K 522, H03K 2108

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active

051265877

ABSTRACT:
A circuit configuration for synchronizing pulse-shaped signals includes a clock-controlled flip-flop having a data input for receiving a pulse-shaped signal to be synchronized, a data output for supplying a synchronized signal, and a clock input. A test circuit has an input connected to the data input of the clock-controlled flip-flop for receiving the pulse-shaped signal to be synchronized, another input for receiving at least one clock signal, and an output connected to the clock input of the clock-controlled flip-flop. The test circuit generates an output signal at the output of the test circuit to be supplied to the clock input of the clock-controlled flip-flop being either equal to or phase-offset relative to the at least one clock signal supplied to the other input of the test circuit. The test circuit ascertains a phase difference between an edge of the pulse-shaped signal to be weighted and a weighting edge of the output signal of the test circuit. The output signal of the test circuit is switched to the other respective clock signal if the phase difference is below a predefined value.

REFERENCES:
patent: 3590280 (1969-11-01), Hudson et al.
patent: 3908084 (1975-09-01), Wiley
patent: 4408333 (1983-10-01), Fujii
patent: 4996444 (1991-02-01), Thomas et al.
IEEE Transactions on Computers, vol. C-25, No. 2, Feb. 1976, pp. 133-139; M. Pechoucek: "Anomalous response times of input synchronizers"; Figure 7.
Tietze Schenk, 8 Auflage, pp. 255-256, Figure 10.49.

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