1991-03-20
1994-01-25
Canney, Vincent P.
Excavating
371 376, 371 377, G06F 1110
Patent
active
052822150
ABSTRACT:
A synchronization circuit for ATM cells transferred in an ATM communication system, wherein the synchronization circuit receives and holds in a bit serial manner the input bit trains constituting the received ATM cells by a shift register unit, performs a CRC operation in a bit serial manner on the held input bit trains by a continuous CRC arithmetic unit in accordance with a simplified CRC operation process different from the usual CRC operation process, and performs the necessary synchronization control upon receiving the CRC arithmetic operation result at a synchronization control unit, thereby enabling CRC arithmetic operations to be performed continuously and by simple hardware on the headers in the ATM cells.
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Hsing, D. P. et al., "On cell size and header error control of asynchronous transfer mode (ATM)", IEEE Global Telecommunications Conference, vol. 1, Nov. 28, 1988, pp. 394-402.
Ely, S. R. et al., "High-speed decoding technique for slip detection in data transmission systems using modified cyclic block codes", Electronic Letters, vol. 19, No. 3, Feb. 3, 1983, pp. 109-110.
European Search Report, The Hague, Nov. 20, 1992.
Hyodo Ryuji
Isono Osamu
Miyamoto Naoyuki
Nishino Tetsuo
Oomuro Katsumi
Canney Vincent P.
Fujitsu Limited
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