Multiplex communications – Wide area network – Packet switching
Patent
1983-12-21
1987-02-24
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
H04J 306
Patent
active
046462910
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The invention relates to a synchronization apparatus in a telecommunication system of the time division multiple (TDM) type in which information is transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules connected to a common bus.
BACKGROUND ART
In order to achieve data transmission correctly in time, signals for synchronizing between transmitter and receiver must also be sent out on a bus.
In known apparatus, as for example in the LM Ericsson Company Description identified by catalogue code X/Yg 118909 Ue relating to the regional processor bus in an AXE 110 telephone exchange, separate clock equipment is utilized for the bus, which means that the information is intentionally delayed and clocked out on the bus with the aid of a separate clock signal unit.
For a combination of transmitter and receiver in the same module, in the above-indicated known apparatus there are required separate clock signals and possibly clock oscillators in both transmitters and receivers for synchronizing with respect to the bus. This results in delay in the information transmission, poor capacity utilization on the bus and a complicated hardware structure. Furthermore, it is difficult to achieve great reliability with central feeding of clock signals.
SUMMARY OF INVENTION
It is an object of the invention to provide an improved telecommunication system of the time division mutliplex type.
To achieve the above and other objects of the invention, there is provided apparatus which includes a bus which is intended for simplex information transmission connected to a plurality of modules, each module including a transmitter and a receiver. An arbitrarily selected module constitutes the master module, and sends synchronizing pulses as well as data to the other modules (slave modules). The synchronizing pulses are used to establish time slots in the TDM system.
With respect to the transmission direction, all the transmitters are successively connected to the starting section of the bus, while all receivers are connected to the final section thereof in the same order as the transmitters. This enables disposing the starting and final sections in parallel conductors in the same cable. The intermediate section of the bus, extending from the last connected transmitter to the first connected receiver is dimensioned such that the delay of information through the bus for transmission from transmitter to receiver in one and the same module, in accordance with the example below, will be at least one time slot or more. The time delay can also be less than one time slot in certain cases. Since the synchronizing pulse and the data information travel the same way, each of the slave modules is synchronized to assume a relative phase position corresponding to its position on the bus. Data is thus clocked-out in the same local clock phase irrespective of the transmitter module, and is clocked-in in the next local clock phase irrespective of receiver module. The one time slot delay through the bus allows the same clock oscillator to be utilized for both transmitter and receiver in a module. The arrangement and dimensioning of the bus enables interference transmission firstly of, information between an arbitrarily selected module pair, and secondly information between a second arbitrarily selected module pair while using two mutually adjacent time slots, and so on until all time slots are occupied.
The advantages of the apparatus provided in accordance with the invention over known apparatus include:
(1) Better bus capacity utilization is obtained by the implementation of the bus and the synchronizing method;
(2) No re-clocking unit on the bus intermediate section is necessary; and
(3) Transmitter and receiver clocks are the same for the respective modules, irrespective of whether a module is a master or a slave, i.e. master and slave are alike, unified hardware thus being obtained.
DESCRIPTION OF FIGURES
The apparatus in accordance with the invention is described i
REFERENCES:
patent: 3732374 (1973-05-01), Rocher et al.
patent: 4498168 (1985-02-01), Tseng
patent: 4503533 (1985-03-01), Tobagi et al.
Perntz Carl-Gunnar E.
Roos Sture G.
Olms Douglas W.
Rokoff Kenneth I.
Telefonaktiebolaget LM Ericsson
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