Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-06-29
2000-09-12
Follansbee, John A.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
711153, G06F 1500
Patent
active
061192155
ABSTRACT:
A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
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Jennings William E.
Kerr Darren
Key Kenneth Michael
Wright Michael L.
Cisco Technology Inc.
Follansbee John A.
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