Synchronization adder circuit

Details Synchronization adder circuit Synchronization adder circuit

1994-09-09

1996-11-12

DeBoer, Todd

Coded data generation or conversion

Phase or time of phase change

Synchro or resolver signal

375324, H03M 148

Patent

active

055744508

ABSTRACT:
A synchronization adder circuit for digital data communication includes an A/D converter, a waveform-shaping circuit, a square circuit, a low-pass filter, and an adder. The A/D converter samples at given sampling points in time per sampling cycle a received signal transmitted through a plurality of subcarriers to digitize sampled values to provide digital signals. The waveform-shaping circuit then waveform-shapes the digital signals from said A/D converter without decomposing them with respect to each subcarrier. The square circuit squares the output signals from the waveform-shaping circuit. The low-pass filter removes a given high-frequency component from output signals from the square circuit. The adder adds values of output signals from the low-pass filter at each sapling point for preselected sapling cycles to determine the samples suitable for reproduction of original data.

REFERENCES:
patent: 4726041 (1988-02-01), Prohaska et al.
patent: 4941155 (1990-07-01), Chuang et al.
patent: 5170413 (1992-12-01), Hess et al.

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