Pulse or digital communications – Synchronizers
Reexamination Certificate
2001-03-12
2004-10-12
Corrielus, Jean B. (Department: 2637)
Pulse or digital communications
Synchronizers
C370S503000
Reexamination Certificate
active
06804314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronism judgment apparatus for judging whether frame synchronization has been established in a transmission system in which frame synchronization with respect to frames as a sequence of slots to which sync patterns are distributed according to the sync patterns, as well as to a communication system where such a synchronism judgment apparatus is applied.
2. Description of the Related Art
Conventionally, in the field of mobile communication, various systems have been constructed in order to deal with differences in transmission information, communication form, service to be provided, etc. And extensive researches and developments have been made to exploit new technologies.
Among those technologies, the CDMA (code division multiple access) is applied positively to next-generation mobile communication systems as a promising wide-band multiple access method because it offers a high degree of confidentiality, has such properties that a communication is less affected by interference/disturbance and fluctuations such as frequency selective fading in radio transmission channel, and enables flexible adaptation to differences of the above kind.
FIG. 10
shows the configuration of an exemplary receiving part that is provided in a radio base station of a CDMA mobile communication system.
As shown in
FIG. 10
, two reception waves I and Q that were subjected in parallel to spreading processing with orthogonal spreading codes in a transmitting end and have occupied bands in a prescribed band (for simplicity, it is assumed here to be a baseband) are supplied to a despreading processing part
61
in parallel. The two outputs of the despreading part
61
are connected to the respective inputs of a detector circuit
62
. Demodulation signals i and q corresponding to the two respective reception waves I and Q are obtained at the two outputs of the detector circuit
62
. The monitoring output and the first to third control outputs of the detector circuit
62
are connected to the first to fourth inputs of a synchronism judgment circuit
70
, respectively. The number of bits Nb (described later) is supplied externally to the fifth input of the synchronism judgment circuit
70
. A synchronism judgment signal is output to the output of the synchronism judgment circuit
70
.
The synchronism judgment circuit
70
is composed of the following components:
A memory
71
in which known sync pattern (hereinafter referred to as “reference bit string”) to be received are stored in advance.
A comparator gate
72
having two inputs that are connected to the output of the memory
71
and the monitoring output of the detector circuit
62
, respectively.
An AND gate
73
having two inputs that are connected to the output of the comparator
72
and the first control output of the detector circuit
62
.
A counter
74
having an enable terminal EN to which the output of the AND gate
73
is connected and a clock terminal CLK and a reset terminal RESET to which the second and third outputs of the detector circuit
62
are connected, respectively.
A comparator
75
having one input to which the output of the counter
74
is connected and the other input to which the number of bits Nb is supplied.
A flip-flop
76
having a clock terminal CLK that is connected to the second output of the detector circuit
62
together with the clock terminal CLK of the counter
74
and a D input that is connected to the third output of the detector circuit
62
together with the reset terminal RESET of the counter
74
.
A flip-flop
77
provided at the final stage and having a D input that is connected to the output of the comparator
75
and a clock terminal CLK that is directly connected to the non-inverting output Q of the flip-flop
76
.
In the conventional example having the above configuration, so that processing for realizing a transmission power control and setting and updating of a variety of transmission rates and transmission forms that are suitable for channel allocation, zone configuration, etc. can be performed repeatedly in time series at a prescribed cycle in each of a mobile station and the radio base station, of the above-mentioned reception waves I and Q, the reception wave Q that is received through a control channel (DPCCH) used for transmission of control information from the mobile station to the radio base station according to a channel control is given as a reception wave that is modulated with a sequence of frames (slots) described below.
As shown in
FIG. 11A
, each slot is composed of four fields containing the following information. The word length of each slot is 10 bits (corresponding to 2,560 chip cycles) irrespective of the values of those fields.
“Pilot bits” to be used as a sync pattern.
“TFCI bits” indicating a communication speed.
“FBI bits” to be used for controlling transmission diversity for a downlink.
“TPC bits” indicating the form of transmission power control to be performed for a downlink.
As shown further in
FIG. 11
, each frame is configured in such a manner that 15 slots (in the maximum case) as described above are packed in order of time series. The length of each frame is 10 ms irrespective of the number of slots actually packed.
As shown in
FIG. 12
, the “pilot bits” field accommodates a known bit string (hereinafter referred to as “sync pattern”) that has a word length of 3 to 8 bits and varies depending on a “slot number” that indicates a packing position of the associated slot in the frame.
Among the bits that constitute each sync pattern, bits that are halftone-dot-meshed in
FIG. 12
will be referred to below simply as “FSW (frame sync-word) bits.”
The despreading processing part
61
performs despreading processing on the above-mentioned reception waves I and Q in parallel. The detector circuit
62
outputs the following demodulation signals i and q by demodulating in parallel two signals obtained by the despreading.
A demodulation signal i indicating, in the form of a sequence of prescribed frames, transmission information (corresponding to a speech signal or the like) received through a data channel (DPDCH).
A demodulation signal q indicating, in the form of a sequence of frames as described above (see FIG.
11
), control information received through a control channel (DPCCH; mentioned above).
In the demodulation processing that is performed in the detector circuit
62
to generate those demodulation signals i and q, phase rotation that has occurred in an upstream radio transmission path from a mobile station to the radio base station is corrected. However, the procedure of such demodulation processing is not an essential feature of the invention and can be realized by using various known technologies, and hence will not be described.
Since the bit string obtained as a demodulation signal q by the above demodulation processing is bit-synchronized with the reception wave Q, the detector circuit
62
performs the following processing by operating independently to divide the bit string according to the above-described frame configuration.
Extracting a bit string that can be regarded as a frame (hereinafter referred to as “interim frame” because it does not necessarily coincide with a true frame) by operating independently to divide the above-mentioned bit string into parts each having the above-mentioned frame word length.
Extracting partial bit strings each of which can be regarded as a sync pattern from the bit string constituting the interim frame according to the frame configuration shown in FIG.
11
B and FIG.
12
. It is assumed that the number of bits included in such a partial bit string conforms to and is proportional to the actual word length (3 to 8 bits) of a sync pattern.
Generating a frame clock signal that rises at the head of the interim frame and a slot enable signal that is an NRZ signal whose logical value becomes “1” only in the periods of valid slots included in the interim frame.
The known bit strings (see
FIG. 12
; hereinafter referred to as “reference bit strings”
Corrielus Jean B.
Fujitsu Limited
Katten Muchin Zavis & Rosenman
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