Television – Synchronization – Sync generation
Reexamination Certificate
2001-04-27
2004-04-27
Kostak, Victor R. (Department: 2611)
Television
Synchronization
Sync generation
C348S521000
Reexamination Certificate
active
06727956
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a sync signal generator circuit for use in visual equipment such as a display apparatus and a recording/reproducing apparatus, and particularly relates to a sync signal generator circuit for generating a sync signal with a stable period.
In general, the sync signal that is used for displaying an image or recording image data in visual equipment is required to have a stable period. However, if the input is in a loss-of-signal state, no sync signal is detected. Further, when TV waves received by an antenna are very weak or immediately after a receiving channel is switched, a period of the sync signal may be temporarily disturbed. For this reason, Japanese Patent Kokai Publication No. 02-177681 published on Jul. 10, 1990 (corresponding to Japanese Patent No.2,584,309), for instance, proposes a method of generating a sync signal with a stable period even if a period of the input sync signal is disturbed.
FIG. 10
is a block diagram showing the prior art sync signal generator circuit disclosed in this publication.
In
FIG. 10
, a reference numeral
22
denotes an input terminal to which a vertical sync signal is inputted,
23
denotes a differentiation circuit for the input vertical sync signal,
24
denotes a gate signal generator,
25
denotes a reset signal generator, and
26
denotes a counter. The differentiation circuit
23
detects a reference edge (namely, a leading edge) of the vertical sync signal inputted to the input terminal
22
, thereby outputting a pulse corresponding to the reference edge. The gate signal generator
24
generates a gate signal on the basis of the output of the differentiation circuit
23
and the outputs of a second comparator
30
, a third comparator
31
, and a loss-of-signal detector
32
, which will be described later. The reset signal generator
25
generates reset pulses on the basis of the outputs of the gate signal generator
24
, the differentiation circuit
23
, and a first comparator
29
, which will be described later. The counter
26
counts clock pulses, and resets the counted value when it receives the reset pulse outputted from the reset signal generator
25
.
Furthermore, in
FIG. 10
, a reference numeral
27
denotes a terminal, and
28
denotes a free-running period selector. To the terminal
27
four control parameters are inputted. The four control parameters consist of the two different parameters that determine timings of opening and closing a gate (not shown) of the reset signal generator
25
and the other two different parameters that determine the free-running period of the output sync signal. The free-running period selector
28
selects either of the two different free-running periods inputted to the terminal
27
in accordance with the output of the loss-of-signal detector
32
, which will be described later.
Moreover, in
FIG. 10
, a reference numeral
29
denotes the first comparator,
30
denotes the second comparator,
31
denotes the third comparator,
32
denotes the loss-of-signal detector,
33
denotes an output control circuit, and
34
denotes an output terminal for the output vertical sync signal. The first comparator
29
compares the output of the counter
26
with the free-running period selected by the free-running period selector
28
. The second comparator
30
compares the output of the counter
26
and one of the parameters inputted to the terminal
27
to detect the timing of closing the gate. The third comparator
31
compares the output of the counter
26
and one of the parameters inputted to the terminal
27
to detect the timing of opening the gate. The loss-of-signal detector
32
detects the state of the input vertical sync signal inputted to the input terminal
22
on the basis of the outputs of the differentiation circuit
23
and the first comparator
29
. The output control circuit
33
prevents the vertical sync signal having too short period from being generated on the basis of the outputs of the reset signal generator
25
, the first comparator
29
, and the second comparator
30
.
The sync signal generator circuit shown in
FIG. 10
works as described below. The differentiation circuit
23
outputs a pulse each time a reference edge of the input vertical sync signal is detected. The gate signal that is outputted from the gate signal generator
24
becomes at a high level after the third comparator
31
detects the timing of opening the gate. Further, the gate signal becomes at a low level after the output of the differentiation circuit
23
goes high, after the second comparator
30
detects the timing of closing the gate thereby bringing its output high, or after the loss-of-signal detector
32
detects a loss-of-signal state thereby bringing its output high. If the output of the gate signal generator
24
is at a low level, the reset signal generator
25
closes the gate and inhibits passage of the output of the differentiation circuit
23
. If the output of the gate signal generator
24
is at a high level, the reset signal generator
25
opens the gate and allows passage of the output of the differentiation circuit
23
, thereby sending it to the counter
26
as a reset pulse of the counter
26
. In addition, the reset signal generator
25
generates a reset pulse also when the first comparator
29
detects that the counted value of the counter
26
reaches a value corresponding to a free-running period selected by the free-running period selector
28
.
Of the four parameters inputted to the terminal
27
, the two different parameters that determine the period of the output sync signal correspond to a vertical period specified in the television signal standard and a little longer period, respectively. The free-running period selector
28
selects the vertical period specified in the standard if the loss-of-signal detector
32
detects a loss-of-signal state, thereby outputting a high level signal. Further, the free-running period selector
28
selects the period a little longer than the vertical period specified in the standard if the loss-of-signal detector
32
outputs a low level signal. The loss-of-signal detector
32
contains shift registers. When the output of the differentiation circuit
23
goes high, a high value is loaded into the first-stage shift register of the loss-of signal detector
32
. Further, when the first comparator
29
detects that the counted value of the counter
26
reaches a value corresponding to the free-running period selected by the free-running period selector
28
, a low value is loaded into the first-stage shift register. Each time a new value is loaded into the first-stage shift register, the values held in the respective shift registers are shifted to the next-stage registers at the same time. Accordingly, if the loss-of-signal state continues for a certain period, values of all shift registers become high. The output of the loss-of-signal detector
32
goes high if all the values of the shift registers are high, and goes low at the other times. The output control circuit
33
inhibits passage of the reset pulse outputted from the reset signal generator
25
between the instant when the first comparator
29
detects that the counted value of the counter
26
reaches a value corresponding to the free-running period selected by the free-running period selector
28
and the instant when the gate is closed by the gate signal generator
24
.
The prior art vertical sync signal generator circuit as described above can suppress the generation of a vertical sync signal having too long or short period, thereby generating a vertical sync signal having a stable period even in the loss-of-signal state.
FIGS. 11A
to
11
D are timing charts indicating the output of the differentiation circuit
23
, the counted value of the counter
26
, the gate signal generated by the gate signal generator
24
, the reset pulses generated by the reset signal generator
25
, the output of the loss-of-signal detector
32
, and the vertical sync signal outputted from the output terminal
34
.
FIG. 11A
shows a cas
Minami Kouji
Suzuki Yoshito
Birch & Stewart Kolasch & Birch, LLP
Kostak Victor R.
Mitsubishi Denki & Kabushiki Kaisha
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