Sync responsive clock generator for digital demodulators

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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Details

307516, 307526, 328134, 331 11, 331 25, 375120, H03L 716, H03L 720

Patent

active

046175261

ABSTRACT:
A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects a synchronization code in the input bit stream to derive the frequency error signal by counting the number of clock pulses present in the period of the detected synchronization code.

REFERENCES:
patent: 3982194 (1976-09-01), Chi et al.
patent: 4003086 (1977-01-01), Larsen et al.
patent: 4023116 (1977-05-01), Alfke et al.
patent: 4131920 (1978-12-01), Berger
patent: 4191976 (1980-03-01), Braun
patent: 4325090 (1982-04-01), Janak et al.

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