Sync chip clamping/sync separator circuit

Details Sync chip clamping/sync separator circuit Sync chip clamping/sync separator circuit

1994-07-21

1996-03-05

Kostak, Victor R.

Television

Synchronization

Sync separation

348532, H04N 508

Patent

active

054972019

ABSTRACT:
Reductions in size and cost for a sync chip clamping/sync separation circuit are envisaged by the use of the CMOS process. The final output amplification section of a differential amplifier circuit is implemented as a P channel FET, and the pull down current for the drain terminal of this P channel FET is set to a value which is smaller than the current which flows when this P channel FET is ON. A constant voltage is supplied by resistors to the non inverting input terminal (+) of the differential amplification circuit. Further, the inverting input terminal (-) of the differential amplification circuit and the output terminal thereof are connected, and also an input coupling capacitor is interposed between the inverting input terminal (-) thereof and an video signal input terminal. Further, a buffer is provided which takes out a sync signal from an input of the P channel FET.

REFERENCES:
patent: 4458212 (1984-07-01), Brehmer et al.
patent: 4484148 (1984-11-01), Wieser et al.
patent: 4893092 (1990-01-01), Okamoto
patent: 4999707 (1991-03-01), Hirao et al.
patent: 5027017 (1991-06-01), Fling
patent: 5045806 (1991-09-01), Yan

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