Synapse cell employing dual gate transistor structure

Details Synapse cell employing dual gate transistor structure Synapse cell employing dual gate transistor structure

1989-10-11

1990-10-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365185, 364513, 364807, H03K 1921

Patent

active

049610023

ABSTRACT:
A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.

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Hollis & Paulos, "Artificial Neurons Using Analog Multipliers", N.C. State University Manuscript Rec'd Dec. 1988.
VLSI for "Artificial Intelligence" by Jose G. Del Gado and Will R. Moore, Kluwer Academic Publishers, 1989, pp. 230-233.
"Programmable Analog Synapses for Micro Electronic Neural Networks Using a Hybrid Digital-Analog Approach" by F. J. Mack et al., IEEE International Conference on Neural Networks, Jul. 24-27, 1988, San Diego, Calif.
"A Pipelined Associative Memory Implemented in VLSI" by Clark et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 1, pp. 28-34, Feb. 1989.

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