Symmetrical multi-layer metal logic array with continuous substr

Details Symmetrical multi-layer metal logic array with continuous substr Symmetrical multi-layer metal logic array with continuous substr

1993-08-26

1995-01-24

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With large area flexible electrodes in press contact with...

257206, 257202, H01L 2210, H01L 2702

Patent

active

053844726

ABSTRACT:
A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

REFERENCES:
patent: 4924287 (1990-05-01), Orbach
patent: 4999698 (1991-03-01), Okuno et al.

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