Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-10-02
1992-06-16
Westin, Edward P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
364784, G06F 750, H03K 1921
Patent
active
051226871
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a circuit arrangement for the EXCLUSIVE-OR linkage of two signals.
U.S. Pat. No. 4,408,134 discloses an XOR gate using ECL [emitter coupled logic] technology in which two inputs A and B are connected with the base terminals of current switching transistors in of superposed pairs of current switches (21, 24 and 25 in FIG. 2 of the patent). The bases of the respective other current switching transistors (22, 23 and 26) are connected with internal reference voltage sources (V.sub.BB1 and V.sub.BB2, respectively). The collector currents of transistors 21 and 23 flow through a common load resistance element 28 at which a voltage signal is dropped that represents the EXCLUSIVE-OR linkage of the signals present at inputs A and B. This output signal travels via an emitter follower 27 to the output node 17 of the XOR gate.
An improved circuit arrangement for the EXCLUSIVE-OR linkage of two signals is shown in FIG. 1. This arrangement is configured in emitter-emitter coupled logic (ECL) technology. But this improved arrangement also has some drawbacks. In order to make these drawbacks clearer in the discussion below, brief reference will be made to the purpose of the individual function blocks.
A first input stage for input signal U.sub.E1 is composed of input transistors EF.sub.1 and EF.sub.2 as emitter followers. A second input stage for input signal U.sub.E2 includes two input transistors EF.sub.3 and EF.sub.4, each connected, at a diode D.sub.1 and D.sub.2 , respectively, to an emitter follower EF.sub.7 and EF.sub.8, respectively. The input stages serve for level matching as well as decoupling of the actual XOR gate from the enabling or driving circuit. The transistors of the input stages each have their collectors connected to ground and, by way of their emitter resistances R.sub.2, R.sub.3 and R.sub.4, to the negative pole of an operating voltage source U.sub.B. The actual XOR gate is composed of current switches which are superposed on one another (series gating). Because of this serial connection, a shift in level is necessary between the two input signals of the actual XOR gate. This is accomplished by the pair of diodes D.sub.1, D.sub.2 and a pair of emitter followers EF.sub.7 and EF.sub.8. In the illustrated embodiment, the potential difference between the two internal signal planes is thus twice the base-emitter voltage.
The mentioned current switches including transistors T.sub.1 to T.sub.6 serve to establish a logic linkage of the two input signals. The lower pair of current switches including transistors T.sub.5 and T.sub.6 are coupled together at their emitters and connected via a current source I.sub.O with the negative pole of the operating voltage source U.sub.B. The base inputs are enabled or driven by the outputs of emitter followers EF.sub.7 and EF.sub.8, respectively. An upper pair of further current switches is connected to each one of the two collector outputs i.sub.5 and i.sub.6. The two base inputs of the first pair T.sub.1, T.sub.2 are enabled or driven by the emitter outputs of the first input stage EF.sub.1 and EF.sub.2, respectively, while the base inputs of the second pair T.sub.3, T.sub.4 are enabled inversely thereto by the emitter outputs of the same mentioned input stage. The four collector outputs of the two upper current switch pairs are connected in parallel by pairs, i.sub.1 with i.sub.3 and i.sub.2 with i.sub.4, and are each connected via load resistance elements R.sub.1 with ground potential (positive potential) of the operating voltage source U.sub.B. The difference output signal can be picked up at these load resistance elements R.sub.1. In order to regenerate the signal levels and to decouple the actual XOR gate from the output, a buffer stage is provided subsequently which, in the illustrated example, is composed of two pairs of emitter followers EF.sub.9, EF.sub.11 and EF.sub.10, EF.sub.12 having emitter resistances R.sub.5, R.sub.6 ; R.sub.5, R.sub.6 that are connected with the negative pole of the operating voltage
REFERENCES:
patent: 3649844 (1972-03-01), Kroos
patent: 3838393 (1974-09-01), Dao
patent: 4041326 (1977-08-01), Robinson
patent: 4408134 (1983-10-01), Allen
patent: 4718035 (1988-01-01), Hara et al.
patent: 4810908 (1989-03-01), Suzuki et al.
patent: 4831579 (1989-05-01), Hara et al.
patent: 4900954 (1990-02-01), Franz et al.
patent: 4924117 (1990-05-01), Tamaru
Elektronik, vol. 36, No. 19, Sep. 18, 1987 (Munchen, DEX) I. Martiny "Grundschaltungen . . . ", pp. 140-146, FIG. 10.
ANT Nachrichtentechnik GmbH
Bertelson David R.
Westin Edward P.
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