Symmetric SRAM cell with buried N+ local interconnection line

Details Symmetric SRAM cell with buried N+ local interconnection line Symmetric SRAM cell with buried N+ local interconnection line

1993-07-28

1994-10-11

Thomas, Tom

Fishing, trapping, and vermin destroying

437 26, 437 48, H01L 2170

Patent

active

053547047

ABSTRACT:
A symmetrical, SRAM silicon device comprises substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no 45.degree. layout, and the metal rule is loose. Pass transistor source and drain regions are in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate adore the gate oxide juxtaposed with the source region and drain region.

REFERENCES:
patent: 4187602 (1980-02-01), McElroy
patent: 4246592 (1981-01-01), Bartlett
patent: 4506436 (1985-03-01), Bakeman, Jr. et al.
patent: 4554729 (1985-11-01), Tamimura et al.
patent: 4608748 (1986-09-01), Noguchi et al.
patent: 4794561 (1988-12-01), Hsu
patent: 4980732 (1990-12-01), Okazawa
patent: 5155055 (1992-10-01), Gill et al.

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