Symmetric segmented memory array architecture

Details Symmetric segmented memory array architecture Symmetric segmented memory array architecture

2002-01-30

2004-03-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S230040

Reexamination Certificate

active

06704217

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory array architectures generally and to symmetric memory array architectures in particular.
BACKGROUND OF THE INVENTION
Memory arrays are well known in the art and comprise matrices of memory cells organized into rows and columns. Each memory cell comprises a source, a drain and a gate, each of which has to receive voltage in order for the cell to be accessed. Columns of sources and columns of drain are connected together by bit lines while rows of gates are connected together by word lines. To activate a cell, one drain bit line, one source bit line and one word line must receive voltage.
A standard memory array architecture consists of one metal line on each column, periodically connected to the underlying bit line via a contact. The contact typically is large and is present within the memory array area. The word line is typically of lower resistance and its contact is located outside of the memory array area. There is typically a common source line for a plurality of memory cells. Furthermore, the metal lines are themselves quite thick. Typically, the distance between bit lines is defined by the width of either or both of the metal lines and the contacts, where the contacts are typically wider than the metal lines.
Various memory array architectures are known which reduce the size of the memory array area by reducing the number of contacts and/or metal lines. In virtual ground architectures, the common ground line is eliminated. Instead, the drain of one cell serves as the source for its neighboring cell. Bit lines are continuous diffusions with a contact to the metal lines every X (8, 16, 24, 32, 64, 128, etc.) cells to reduce resistance. The gain in area is up to 40% due to the reduced number of contacts and the elimination of the common source line.
To further reduce array size, the alternate metal, virtual ground architecture (AMG), described in U.S. Pat. No. 5,204,835, has two bit lines per metal line. Typically, in the AMG architecture, the cell size is close or equal to the minimum feature size possible for the cells.
Standard virtual ground architectures access every cell symmetrically (i.e. every bit line receives voltage directly from a metal line). The AMG architecture, which is more compact than standard virtual ground architectures, directly provides voltage to the metalized bit lines but indirectly provides voltage to the segmented, non-metalized bit lines. As a result, the voltage on an activated non-metalized bit line (which is provided through n-channel select transistors) is lower than the voltage on a simultaneously activated metalized bit line. Furthermore, n-channel transistors are not good at passing the high voltages needed for programming.
The non-symmetry of the AMG architecture makes it difficult to use with a nitride read only memory (NROM) array which stores two bits in each NROM cell. Such a cell is described in Applicant's copending U.S. application Ser. No. 08/905,286, filed Aug. 1, 1997 entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” and assigned to Saifun Semiconductors, the same assignee as for this application, whose disclosure is incorporated herein by reference. The two bits in a cell are located of each side of the cell and each bit is accessed by voltages on the two neighboring bit lines of the cell. Accordingly, the cell requires that its two neighboring bit lines receive equivalent amounts of voltage thereby to read both bits equally (although not simultaneously).
Some architectures segment the bit lines. Each row of segmented bit lines is called a “block” and each block typically includes block select transistors to activate only one block at a time. This is particularly important for FLASH electrically erasable, programmable, read only memory (FLASH EEPROM) arrays which pass high voltages along the bit lines during programming and erase operations. During programmming, the bit line voltages disturb the unselected cells.
To reduce the total time the programming voltage disturbs the cells, the bit lines are segmented into small blocks.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a symmetric architecture for memory cells.
In one embodiment, the memory array includes a plurality of diffusion bit lines, a plurality of select transistors and even and odd types of metal bit lines. There is one select transistor per diffusion bit line, the select transistors being of first, second, third, fourth, fifth, sixth, seventh and eighth types. The odd metal bit lines are connectable to the first, third, fifth and seventh select transistor types and the even metal bit lines are connectable to the second, fourth, sixth and eighth select transistor types.
Moreover, in accordance with a preferred embodiment of the present invention, the division bit lines have first and second ends and wherein the second, fourth, sixth and eighth types of select transistors are connected at the second ends of their associated diffusion bit lines and the first, third, fifth and seventh types of select transistors are connected to the first ends of their associated diffusion bit lines.
Further, in accordance with a preferred embodiment of the present invention, the array also includes even and odd contact bit lines, connectable to the even and odd types of metal bid lines, respectively, wherein the second, fourth, sixth and eighth types of select transistors are connected to the even contact bit lines and the first, third, fifth and seventh types of select transistors are connected to the odd contact bit lines.
Still further, in accordance with a preferred embodiment of the present invention, the memory array includes pairs of segmenting select transistors adapted to access a segment of eight diffusion bit lines, wherein a first segmenting select transistor of a segment is connected between select transistors of a segment and a first metal bit line and a second segmenting select transistor of the segment is connected between the select transistors of the segment and a neighboring metal bit line to the first metal bit line.
In accordance with a preferred embodiment of the present invention, the memory array includes nitride read only memory (NROM) cells.
In accordance with a further preferred embodiment of the present invention, the select transistors may be low threshold voltage devices. Alternatively, they may have a channel length shorter than a standard channel length of a process.
There is also provided, in accordance with a preferred embodiment of the present invention, a memory array which includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors, wherein there are more than two diffusion bit lines per metal bit line.
Further, in accordance with a preferred embodiment of the present invention, there are more select transistors than diffusion bit lines.
Still further, in accordance with a preferred embodiment of the present invention, there can be four or eight diffusion bit lines per metal bit line.
In an alternative embodiment the second plurality is not a multiple of two. It can be an odd plurality.


REFERENCES:
patent: 5590068 (1996-12-01), Bergemont
patent: 6351415 (2002-02-01), Kushnarenko

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