Symmetric multiprocessing computer with non-uniform memory acces

Details Symmetric multiprocessing computer with non-uniform memory acces Symmetric multiprocessing computer with non-uniform memory acces

1996-08-12

1999-03-23

An, Meng-Ai T.

395312, 395403, 395553, G06F 1300, G06F 112

Patent

active

058871462

ABSTRACT:
A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

REFERENCES:
patent: 5269013 (1993-12-01), Arbramson et al.
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5577204 (1996-11-01), Brewer et al.
patent: 5603005 (1997-02-01), Bauman et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
Oswell, John, Computing Canada, Looking ahead to ccNUMA, May 9, 1996, vol. 22, No. 10, pp. 42 (1).
Lenoski, D. et al., The Directory-Based Cache Coherence Protocol for the Dash Multiprocessor, Chap. 2887, pp. 148-159, Aug. 1990.
Kontothanassis, L., et al., University of Rochester, Software Cache Coherence for Large Scale Multiprocessors, Mar. 1994.
Stenstrom, P., et al., Computer Systems Laboratory, Comparative Performance Evaluation of Cache Numa and Coma Architectures, vol. 20, No. 2, May 1992.
Singh, J., et al., Computer Systems Laboratory, Stanford University, An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford Dash Multiprocessors, AMC, pp. 214-225, 1993.
Chapin, J., et al., Computer Systems Laboratory, Memory System Performance of UNIX on CC-NUMA Multipurposes, vol. 23, No. 1, May 1995.
Bolosky, W., et al., Numa Policies and Their Relation to Memory Architecture, ACM, pp. 212-221, Sep. 1991.
Lovett, T., et al., Sequent Computer Systems, Inc., Sting. A CC-NUMA Computer System for the Commercial Marketplace, ISCA, pp. 308-317, Mar. 1996.
Lenoski, D., et al., Computer Systems Laboratory, The Stanford Dash Multiprocessor, pp. 63-79, Mar. 1992.
Lenoski, D., et al., IEEE Transactions on Parallel and Distributed Systems, The Dash Prototype: Logic Overhead and Performance, vol. 4, No. 1, Jan. 1993.
Lenoski, D., et al., Computer Systems Laboratory, The Directory-Based Cache Coherence Protocol for the Dash Multiprocessor, Chap. 2887, pp. 148-159, Aug. 1990.
Senthil, K., Journal of Parallel and Distributed Computing, A Scalable Distributed Shared Memory Architecture, vol. 23, pp. 547-554, 1994.
Kontothanassis, L., Journal of Parallel and Distributed Computing, High Performance Software Coherence for Current and Future Architectures, vol. 29, pp. 179-195, 1995.
Hitoshi, O., Transactions of Information Processing Society of Japan, Performance Analysis of a Data Diffusion Machine with High Fanout and Split Directories, vol. 36, No. 7, pp. 1662-1668, Jul. 1995.
Nowatzk, A., et al., Parallel Computing: Trends and Applications, Exploiting Parallelism in Cache Coherency Protocol Engines, Grenoble France, pp. 269-286, Sep. 1993.
Haridi, S., et al., Euro-Par '95 Parallel Processing, Experimental Performance Evaluation on Network-based Shared-memory Architectures, pp. 461-468, 1994.
Sevcik, et al., Computer Systems Research Institute, Performance benefits and limitations of large Numa multiprocessors, pp. 185-205, 1994.
Dewan, et al., Southern Methodist University, A Case for Uniform Memory Access Multiprocessors, pp. 20-26.
Li, et al., Cornell University, Access Normalization: Loop Restructuring for Numa Computers, vol. 11, No. 4, pp. 353-375, Nov. 1993.
Agarwal, et al., Massachusetts Institute of Technology, The MIT Alewife Machine: Architecture and Performance, pp. 2-13, 1995.
Chan, Tony, Ninth Annual International Conference, Application of the Scalable Coherent Interface in Multistage Networks, pp. 370-377, 1994.
Cukic, et al., Uiversity of Houston, The Performance Impact of False Subpage Sharing in KSR1, pp. 64-71, 1995.
Al-Mouhamed, Transaction of Parallel and Dsitributed Systems, Analysis of Macro-Dataflow Dynamic Scheduling on Nonuniform Memory Access Architectures, vol. 4, No. 8, pp. 875-888, Aug. 1993.
Wolski, et al., Journal of Parallel and Distributed Computing, Program Partition for Numa Multiprocessor Computer Systems, vol. 19, pp. 203-218, 1993.
Choe, et al., Seoul National University, Delayed Consistency and Its Effects on the Interconnection Network of Shared Memory Multiprocessors, pp. 436-439.
Sivasubramaniam, et al., Abstracting Network Characteristics and Locality Properties of Parallel Systems, pp. 54-63, 1995.
Abdelrahman, et al., University of Toronto, Distributed Array Data Management on Numa Multiprocessors, pp. 551-559, 1994.
LaRowe, et al., Transactions on Parallel and Distributed Systems, Evaluatin of Numa Memory Management Through Modeling and Measurements, vol. 3 No. 6, Nov. 1992.
LaRowe, et al., ACM, The Robustness of Numa Memory Management, pp. 137-151, 1991.
Wilson, A., Jr., ACM, Encore Computer Corporation, Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors, pp. 244-252, 1987.
Kuskin, et al., Computer Systems Laboratory, The Stanford Flash Multiprocessor, pp. 302-313, 1994.
Chandra, R., et al., Computer Systems Laboratory, Scheduling and Page Migration for Multiprocessor Compute Servers, pp. 12-24, 1994.
Chaiken, D., et al., Massachusetts Institute of Technology., Limitless Directories: A Scalable Cache Coherence Scheme, pp. 224-234, 1991.
Brown, D., Convex Delivers Beta Appetizers, pp. 1-15, 1994.
Shreekant, et al., New Directions, Scalable Shared-Memeory Multiprocessor Arachitectures, pp. 71-74, Jun. 1990.
Singh, et al., Computer, Scaling Parallel Programs for Multiprocessors: Methodology and Examples, pp. 42-50, 1993.
Singh, et al., Computer Systems Laboratory Stanford University, Load Balancing and Data Locality in Hierarchial N-body Methods, pp. 1-21.
Brown, D.H., KSR: Addressing The MPP Software Hurdle, pp. 1-18, Dec. 1993.

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