Multiplex communications – Duplex – Duplex repeaters or extenders
Reexamination Certificate
1997-05-16
2001-09-25
Olms, Douglas (Department: 2661)
Multiplex communications
Duplex
Duplex repeaters or extenders
C370S229000, C370S412000, C375S211000, C710S107000
Reexamination Certificate
active
06295281
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
Ethernet is a local-area network (LAN) design which employs carrier sense multiple access with collision detection (CSMA/CD) as an access control method. When a device wishes to transmit a packet on the LAN, it first listens to the network to determine if any other device is currently transmitting, and waits if the network is busy. Otherwise, the device begins transmitting its packet, while simultaneously listening to the bus to determine if the packet collided with other network traffic. If such a collision is detected, the device ceases transmission, then checks for an idle network again before retransmitting.
An Ethernet repeater is a network element which provides a common point for receiving packets from individual devices and for retransmitting the packets to other devices. A buffered repeater must be employed when full duplex links are used. An Ethernet buffered repeater provides temporary storage of received packets prior to transmission to all other interconnected devices. However, the discrete amount of memory available for queuing received data can be filled. To address this situation, the architecture for the Ethernet buffered repeater uses a flow control technique specified by the IEEE 802.3x standard. According to this architecture, a buffered repeater port which is receiving packets transmits a flow control frame to the transmitting port at the other end of the respective link to suspend packet transmissions to the repeater for some specified period of time when the buffered repeater port can no longer receive additional incoming packets, presumably because its receive buffer is filling up.
This architecture also provides for a discrete buffer space at each transmit port. However, this buffer space can also be filled. When the port at the other end of the respective link can no longer receive data from such a buffered repeater transmit port, the respective receiving port transmits a flow control frame to the buffered repeater, and in response the buffered repeater transmit port is required to suspend the transmission of data.
Due to the high transmission speeds utilized in the next generation of Ethernet, known as Gigabit Ethernet, repeater buffer spaces can easily be filled before feedback can be provided to a source for slowing or temporarily stopping the flow of data into the repeater. This necessitates the inefficient retransmission of incompletely received packets.
Previous approaches adhering to the IEEE 802.3x standard have required the provision of a relatively large transmit FIFO buffer in order to allow the transmit data to queue up while the link is thus disabled. However, it is generally acknowledged that it is not cost-effective for a buffered repeater to support both large transmit and receive queues. One proposal for addressing this situation prohibits buffered repeater transmit ports from being flow-controlled off. In other words, such buffered repeater transmit ports are not to respond to received flow control frames. Each buffered repeater receive port is therefore allowed to send flow control frames to a respective remote port as the receive queue fills, but the respective buffered repeater transmit port does not accept flow control frames from the remote port due to remote congestion. Such a proposal has been labelled Asymmetric Flow Control, and necessarily implicates packet loss due to downstream congestion, retransmission of the lost packets, and consequent reduction in available bandwidth.
Therefore, buffered repeaters, which meet the applicable industry standard, have heretofore been unable to accommodate high-rate Ethernet traffic without either large transmit buffer spaces or the inefficient loss and retransmission of packets associated with Asymmetric Flow Control.
BRIEF SUMMARY OF THE INVENTION
The presently disclosed method and apparatus enables symmetric flow control in a buffered repeater according to IEEE 802.3x without implicating packet loss due to ignored flow control frames, and without requiring the provision of a relatively large transmit queue. This method and apparatus is applicable in particular to Gigabit Ethernet LAN applications, though the concept of the method and apparatus are suitable for use at other rates and in other environments.
An Ethernet full duplex buffered repeater according to the present invention includes a media access controller (MAC) associated with each port to parse the packets received, and a FIFO buffer memory associated with a receive portion of each full duplex port to buffer received packets. IEEE 802.3x flow control techniques are employed to keep the FIFOs from overfilling. An internal arbitration mechanism is used to allow each of the respective receive FIFOs to have a turn transmitting data over a local bus to the remaining transmit ports in a round-robin fashion. A transmit FIFO buffer memory associated with the transmit portion of each full duplex port is employed to buffer data for the transmit port, though this transmit FIFO is reduced to a relatively small size.
In a first embodiment, four repeater ports are associated with each buffered repeater device, and all of the associated FIFOs and logic necessary to implement the repeater are fabricated within the device. Each device is cascadable with other such devices to enable implementation of an arbitrarily large buffered repeater, in increments of four ports. The present device is capable of interfacing directly to industry standard 10:1 Serializer/Deserializer (SERDES) devices which in turn interface to optic or copper physical layer devices.
The present buffered repeater enables the support of symmetric flow control without the requirement of a relatively large transmit queue. As the receive queues store data, the arbitration mechanism controls which of the receive queues having data will transmit the data over the local bus within the buffered repeater. All of the other ports, that is to say the ports other than the one transmitting data over the local bus, take the transmitted data off the local bus and transmit it out across the respective links to which each port is connected.
Each of the MACs monitors the incoming data stream for Pause Frames received as a result of a respective receiving device being unable to accommodate data being transmitted from the buffered repeater port. When a Pause Frame is received at a port, the MAC starts a pause counter as specified in the standard implementation of IEEE 802.3x Flow Control. In addition, this port asserts an output signal, BUS_XOFF. By implementing this signal as an open collector output and asserting the signal by pulling it low, all of the BUS_XOFF signals, from each of the ports, are logically OR'd together; when any one of the ports pulls this signal low, the BUS_XOFF signal is asserted for the device. Each of the receive ports monitors the state of this signal line, and no port will initiate the transmission of a packet over the local bus when this signal is asserted low. Thus, when any one port is required to suspend data transmission, the transfer of data within the repeater is suspended. As the receive FIFOs fill, Pause Frames are issued by the respective MAC over each associated link. This is consistent with existing layer
1
devices in which an overloaded port holds off the shared media by causing artificial collisions.
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“Gigabuffer Repeater Proposal”, Packet Engines Incorporated proposal, Sep. 7, 1996.
“Gigabit Buffered Distributor Proposal”, Packet Engines Incorporated proposal, Nov. 21, 1996.
Hiscock James S.
Itkowsky Frank A.
Robins Cary B.
3Com Corporation
Olms Douglas
Phunkuch Bob A.
Weingarten, Schurgin Gagnebin & Hayes LLP
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