Symmetric clock system for a data processing system including dy

Details Symmetric clock system for a data processing system including dy Symmetric clock system for a data processing system including dy

1995-08-10

1996-06-04

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

H03K 2100

Patent

active

055240356

ABSTRACT:
A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

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patent: 5313509 (1994-05-01), Tomita
patent: 5371772 (1994-12-01), Al-Khairi

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