Symmetric clock receiver for differential input signals

Details Symmetric clock receiver for differential input signals Symmetric clock receiver for differential input signals

2000-06-21

2001-09-25

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S299000, C327S172000

Reexamination Certificate

active

06294940

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to clock receivers and more particularly, to clock receiver circuits, which receive fully differential clock signals and create controlled clock pulses from each transition.
2. Description of the Related Art
Higher clock rates for clock devices, such as clock receivers, are desired in integrated circuits where performance criteria is increased from one generation of devices to the next. For example, with the advent of double data rate (DDR) synchronous dynamic random access memory (SDRAM) new requirements for the clock receiver arise. These goals include:
A: The delay matching between a rising clock edge to an internal clock with a falling clock edge to an internal clock (with double rate) becomes more important; and
B: The AC-impedance of positive and negative clock input pins should match very well.
Referring to
FIG. 1
, a standard differential amplifier based receiver
10
does not fulfill requirements A and B very well. The impedance of the internal nodes OUTN and OUTP differ by orders of magnitude so the effect of Miller-coupling is much larger for input VINP (e.g., CK). (For large systems, this makes it difficult for a System Clock driver to supply a good symmetric clock signal).
As shown in
FIG. 2
, clock signals CK and /CK are received by differential amplifier
20
. Pulse generator circuits
22
use a pulse created from a positive edge, and this pulse, together with a pulse created from a inverted negative edge (by inverter
23
), are used (by employing an OR function
24
) to create a double data rate pulse. This structure, however, may not satisfy goals A and B in every case. The circuit of
FIG. 2
includes an additional inverter
23
, which can create timing mismatches.
To attempt to fulfill goals A and B, structures such as the one illustratively shown in
FIG. 3
have been proposed. This structure includes two differential amplifiers
30
. The CK and /CK signals are input to opposite input nodes of each amplifier
30
. Pulse generators
32
create pulses on each rising edge of the output of the amplifiers
30
. The outputs are ORed by OR function
34
to provide a double rate output. The drawback of this structure is the high current consumption (due to the second pulse generator and second amplifier) and the two separate pulse generators
32
used give rise to timing mismatches.
Therefore, a need exists for a clock receiver, which provides symmetric or matched delay output clock pulses and minimizes power consumption.
SUMMARY OF THE INVENTION
A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.
In alternate embodiments, the first circuit stage may include a differential amplifier. The differential amplifier may include a current mirror for generating a first current to generate the first and second outputs signals. The current mirror may include a first current mirror portion which generates the first output signal and a second current mirror portion which generates the second output signal wherein the first and the second current mirror portions are selectable in accordance with the control signal. The differential amplifier may include a direct current load for generating a first current to generate the first and second outputs signals. The differential amplifier may include a first current source for generating a first current to generate the first and second outputs signals and a second current source for generating a second current such that hysteresis at the output of the second circuit stage is controlled. The hysteresis may be given by H =(I
first
−I
second
/2)/gm where I
first
is the first current, I
second
is the second current and gm is the transconductance of the differential amplifier.
The clock pulses are preferably generated for both rising and falling edges of the input clock signals. The circuit may include a driver coupled to the switch, and the driver may include transfer gates driven by the output of the second stage, the driver for generating the control signal for the switch. The pulse shaper may include a self-resetting pulse generator. The first circuit stage may include a fully differential current mirror amplifier. The first circuit stage may include a differential amplifier with a folded cascode load.
A double data rate clock circuit, in accordance with the present invention, includes a first circuit stage including a differential amplifier for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals, and the first stage includes a transfer gate for switching an output polarity by selecting one of the first output signal and the second output signal generated by the differential amplifier in accordance with a control signal. A second circuit stage is coupled to the first circuit stage, and the second circuit stage includes a pulse generator for receiving the first output signal and the second output signal and generating clock pulses to be output from the pulse generator in accordance with the first output signal and the second output signal. A toggle switch generates the control signal based on an output of the pulse generator.
In other embodiments, the differential amplifier may include a current mirror for generating a first current to generate the first and second outputs signals. The current mirror may include a first current mirror portion which generates the first output signal and a second current mirror portion which generates the second output signal wherein the first and the second current mirror portions are selectable in accordance with the control signal. The differential amplifier may include a direct current load for generating a first current to generate the first and second output signals. The differential amplifier may further include a first current source for generating a first current to generate the first and second output signals and a second current source for generating a second current such that hysteresis at the output of the second circuit stage is controlled. The hysteresis may be given by H =(I
first
−I
second
/2)/gm, where I
first
is the first current, I
second
is the second current and gm is the transconductance of the differential amplifier. The clock pulses are preferably generated for both rising and falling edges of the input clock signals. The toggle switch may include transfer gates driven by the output of the second circuit stage, and the driver generates the control signal for the transfer gates. The pulse generator may include a self-resetting pulse generator. The first circuit stage may include a folded cascode load differential amplifier. The first circuit stage may includes a fully differential current mirror amplifier.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 3828347 (1974-08-01), Sacks et al.
patent: 4906943 (1990-03-01), Koch
patent: 5467089 (1995-11-01), Draxelmayr
patent: 5719576 (1998-02-01), Draxelmayr
patent: 6023615 (2000-02-01), Bruckert et al.
patent: 6043694 (2000-03-01), Dortu

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