Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2003-05-28
2004-11-23
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06822513
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to analog circuits, and more specifically to Complementary Metal-Oxide-Semiconductor (CMOS) differential amplifiers.
2. Background and Related Art
Analog circuits have revolutionized the way people work and play and have contributed enormously to the advancement of humankind. A key component of many analog circuit designs is the amplifier. A differential amplifier has two input terminals and at least one output terminal. In a differential-input to single-output amplifier, the differential amplifier generates a signal at its output terminal that has a magnitude that is roughly proportional to the difference between the magnitudes of the signals at its input terminals. In the differential-input to differential-output amplifier, the differential amplifier generates a signal on its two output terminals such that the difference between the magnitudes of the output signals is roughly proportional to the difference between the magnitudes of the input signals.
CMOS differential amplifiers are constructed of a number of interconnected transistors. Some transistors are of one carrier type often called n-type Field Effect Transistors (i.e., nFETs), while other transistors are of the opposite carrier type often called p-type Field Effect Transistors (i.e., pFETs). In normal operation, Field Effect Transistors (FETs) generally have two modes of operation, linear and saturation. The mode of operation for a specific FET will depend on the voltages applied on its source, drain, and gate terminals as well as its threshold voltage.
The proper functioning of the CMOS differential amplifier often depends heavily on ensuring that at least some of the FETs are operating in a particular mode of operation. In order to ensure this, it is often necessary to generate a particular bias voltage that is different than the high and low voltages (often termed Vdd and Vss, respectively) that are supplied to the circuit as a whole. The particular bias voltage(s) are then applied to the gate terminals of the appropriate FETs.
In conventional CMOS differential amplifiers, separate voltage biases are used for the current source FETs, current load pair FETs, and cascode stage FETs. Furthermore, separate bias voltages may be used for FETs of different carrier types (i.e., n-type versus p-type). Accordingly, bias mechanisms for conventional CMOS differential amplifiers may be quite complex thereby using excessive layout area and increasing overall power consumption. Furthermore, the external biases often do not work under all circumstances. For instance, an external bias for the cascode transistors in complementary cascode structures rarely works because the gain and output resistance of a differential amplifier may both be very high and difficult to model accurately.
Other conventional CMOS differential amplifiers use self-biasing mechanisms that incorporate negative feedback. However, in those mechanisms, either the transistors for current sources or loads are biased in their linear mode instead of the saturation mode. This results in reduced voltage gain. Alternatively, the bias current level achieved using reasonable size of transistors is too small to obtain usable gain, especially when the supply voltage is small. Another negative impact is that when the input slew rate is high, because of the complicated interaction between the self-biasing and other parts of the circuitry, the proper operation of the amplifier can bc disabled.
Accordingly, what would be advantageous is a CMOS differential amplifier that allows for a more simplified biasing mechanism.
BRIEF SUMMARY OF THE INVENTION
The foregoing problems with the prior state of the art are overcome by the principles of the present invention which are directed towards a complementary CMOS differential amplifier that includes two differential amplifiers.
A first differential amplifier includes two input n-type Field-Effect Transistors (nFETs) having gate terminals coupled to the input terminals of the complementary differential amplifier. Two current load p-type Field-Effect Transistors (pFETs) are each coupled in series between a high voltage source and a drain terminal of a respective input nFET. A current source nFET is coupled in series between a common source terminal of the two input nFETs and a low voltage source.
A second differential amplifier includes two input pFETs having gate terminals also coupled to the input terminals of the complementary differential amplifier. Two current load nFETs are each coupled in series between the low voltage source and a drain terminal of a respective input pFET. A current source pFET is coupled in series between a common source terminal of the two input pFETs and the high voltage source.
This configuration allows for a far less complex biasing mechanism than conventional CMOS complementary differential amplifiers. The biasing mechanism may include a single diode-connected nFET and a single diode connected pFET. The drain terminal of the bias nFET and the bias pFET are coupled together. The source terminal of the bias pFET is coupled to the high voltage source, while the source terminal of the bias nFET is coupled to the low voltage source. In order to properly bias, the gate terminal of the bias pFET is coupled to the gate terminals of the two current load pFETs and to the current source pFET. The gate terminal of the bias nFET is coupled to the gate terminals of the two current load nFETs and to the current source nFET.
Accordingly, since only two bias transistors are needed to provide all of the bias voltage, the biasing mechanism is less complex and requires less design layout and draws less current. Also, in this configuration, the biased FETs operate in the saturation region for all input voltages, thereby guaranteeing high gain and low power consumption.
A complementary folded cascode stage may be added to this complementary different amplifier to further increase gain. The folded cascode stage includes two nFETs and two pFETs. The source terminals of the two cascode pFETs are each coupled to a drain terminal of a respective current load pFET. The source terminals of the two cascoded nFETs are each coupled to a drain terminal of a respective current load nFET. The gate terminals of each of the four cascode FETs are shared in common and coupled to the drain terminals of one of the cascode pFET and NFET pairs. In this configuration, no additional biasing voltage is needed while the cascode FETs operate in a guaranteed saturation region. The drain terminal of one of the cascode pFETs is coupled to the drain terminal of one of the cascode nFETs. The drain terminal of the other cascode pFET is coupled to the drain terminal of the other cascode nFET.
An inverter stage may be added in which the gate terminal of the inverter FETs are coupled to each other and to the common drain terminal of one of the cascode pFET and nFET pairs.
This configuration has other advantages in addition to the reduced complexity of the bias mechanism mentioned above. For example, the complementary CMOS differential amplifier has a high common-mode rejection ratio, a cascode stage that has reduced sensitivity to variations in supply voltage, process and temperature. Furthermore, the differential amplifier has rail-to-rail common mode range.
In particular, when the input common-mode is above mid-rail (i.e., above the average of the high voltage source and the low voltage source), the first differential amplifier provides most of the gain of the complementary CMOS differential amplifier. On the other hand, when the input common-mode is below mid-rail, the second differential amplifier provides most of the gain of the complementary CMOS differential amplifier. The further gain provided by the cascode stage significantly reduces the bias current needed to maintain a high speed. This further reduces power consumption even for high speed applications. The inverter may be used to drive a rail-to-rail output to thereby drive digital circuitry.
Additional features
Li Zhongmin
Rasmussen Bryce
AMI Semiconductor Inc.
Choe Henry
Workman Nydegger
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