Symbol timing recovery circuit in digital demodulator

Details Symbol timing recovery circuit in digital demodulator Symbol timing recovery circuit in digital demodulator

1997-09-30

2000-04-25

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375222, 375350, 341 61, 327141, H04L 700

Patent

active

060552840

ABSTRACT:
A symbol timing recovery circuit in a digital demodulator is disclosed. The symbol timing recovery circuit comprises means for generating a clock signal in a predetermined period, means for sampling a received signal according to the clock signal, an interpolator for interpolating the output signal from the sampling means according to a filter tap coefficients calculated by a fractional interval at each sampling period to obtain an interpolant, a data filter for filtering the interpolant and providing the filtered interpolants as a strobe data, a timing error detector for detecting a timing error from the strobe data to generate a timing error signal, a loop filter for filtering the timing error signal to obtain and provide a mean timing error signal; and a controller for providing the fractional interval and controlling the signal processing operation of the data filter, timing error detector, and loop filter according to the mean timing error signal. By having this structure, the data filter, timing error detector and loop filter perform a signal processing according to the valid interpolant of the interpolant outputs from the interpolator, hence the symbol timing recovery circuit in the digital modulator can be simplified.

REFERENCES:
patent: 4692931 (1987-09-01), Ohsawa
patent: 4707841 (1987-11-01), Yen et al.
patent: 5612975 (1997-03-01), Becker et al.
patent: 5724396 (1998-03-01), Claydon et al.

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