Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Patent
1997-08-11
1999-11-23
Chin, Stephen
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
713400, 713401, 713503, H04L 700
Patent
active
059913479
ABSTRACT:
A symbol timing recovery circuit for a base band communication system having a plurality of channels includes a main ADC-STR (analog to digital converter - symbol timing recovery) unit and a plurality of sub ADC-STR units. The main ADC-STR detects a timing error of a first received signal and uses the detected value as a sampling signal of the first received signal. The plurality of sub- ADC-STR units compares the sampling signal generated from the main ADC-STR unit and a symbol timing signal following the first receive signal. Each of the sub ADC-STR units delays the sampling signal in accordance with the compared value for a predetermined time. The delayed signal is used as a sampling signal. The circuit employs a voltage-controlled oscillator VCO in a main ADC-STR circuit, but a VCO is not used in the sub- ADC-STR circuits, so as to delay an output signal of the main ADC-STR circuit and achieve a phase locked loop. Hence, mutual interference between the voltage-controlled oscillators is avoided.
REFERENCES:
patent: 5724397 (1998-03-01), Torsti
patent: 5859671 (1999-01-01), Kim
patent: 5914986 (1999-06-01), Ohta et al.
Chun Byung Jin
Kim Beom Sup
Chin Stephen
Ghayour Mohammad
LG Semicon Co. Ltd.
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