Symbol timing recovery based on complex sample magnitude

Details Symbol timing recovery based on complex sample magnitude Symbol timing recovery based on complex sample magnitude

1995-06-06

1997-09-23

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

328 72, H04L 700

Patent

active

056712570

ABSTRACT:
A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.

REFERENCES:
patent: 4704582 (1987-11-01), Dixon et al.
patent: 4941155 (1990-07-01), Chuang et al.
patent: 5151920 (1992-09-01), Haagh et al.
patent: 5440265 (1995-08-01), Cochran et al.
EDN "Undersmapling Reduces data-acquisition costs for Select Applications" by jeff Kristen et al., pp. 217-228 1990.
"Timing Recovery in Digital Synchronous Data Receivers" Mueller and Muller, IEEE Trans. On Comm. vol. 24, No. 5 May 1976.
"Interpolation in Digital Modems -Part II: Implementation and Performance. Erup, Gardner, Harris, IEEE " vol.41 No. 6 Jun. 1993.
"Intepolation in Digital MOdems-Part I: Fundamentals Gardner, IEE Trans. on Comm " vol. 41, No. 3, Mar. 1993.
"Symbol Synchronizer Performance affected by Non-Ideal Interpolation in Digital Modems in Digital Modems" Bucket and Moeneclaey, IEEE 0-7803-1825 04.
The Performance of Two Symbols Timing Recovery Algorithms for PSK Demodulators. Cowley and Sabel, IEEE 0090-678/94 1994.
A Continuously Variable Digital Delay Element. Farrow, C.W. IEEE CH2458-8-88-0000-2641 1988.
A New Variable Fractional Sample Delay Filter with Non-Linear Interpolation. Liu & Wei. IEEE Trans vol. 39 No. 2 1992.
The Effect of Interpolation on the BER Performance of Narrowbank BPSK and (O) QPSK on Rician-FAding Channels Bucket and Moeneclaey. IEEE Trans on Comm. vol 42 #11 Nov. 1994.
On Sampling Rate, Analog Prefiltering, and Sufficient Statistics for Digital Receivers. Meyr, Oerder, Polydoros IEEE Trans on Comm. vol. 42 No. 12, Dec. 1994.

Affiliated with

Also associated with

Rating

Symbol timing recovery based on complex sample magnitude does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Symbol timing recovery based on complex sample magnitude, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Symbol timing recovery based on complex sample magnitude will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1941188