Symbol-quality evaluation in a digital communications receiver

Details Symbol-quality evaluation in a digital communications receiver Symbol-quality evaluation in a digital communications receiver

1998-05-13

2001-04-03

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

06212246

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electronic communication and, more particularly, to symbol-clock recovery in a digital receiver.
2. Description of the Related Art
Electronic communication is generally accomplished through a carrier wave that is modulated to bear data from a transmitting unit to a receiving unit. The transmission of digital data involves several steps, including partitioning the data into a sequence of symbols, modulating the carrier wave with the sequence of symbols to produce the transmitted signal, and propagating the transmitted signal through a communication channel. The received signal is received by the receiver which demodulates it to extract the received symbols. Finally, the receiver quantizes the symbols to reproduce the transmitted digital data.
An important component of the receiver is a symbol clock used in demodulating the received signal and quantizing the symbols. The symbol clock generates a signal at the symbol rate of the received signal. The symbol clock indicates the boundaries between symbols in the received signal, and is an important input to various elements in the receiver such as matched filters, differential decoders, and slicers. If the symbol clock signal deviates from the correct timing of the symbol boundaries, the function of all of these components is degraded, increasing the receiver's error rate. It is therefore helpful to have a system for evaluating the symbol clock and detecting drifts in its phase from the timing of the symbol sequence.
Prior-art symbol-timing recovery circuits use open-loop synchronizers, which use no feedback to the symbol clock, and closed-loop synchronizers, which test small shifts in the symbol timing for improved symbol synchronization and adjust the symbol clock accordingly. The closed-loop synchronizers, such as early/late-gate loops and tau-dither loops, generate error signals indicative of the phase offset between the symbol boundaries and the symbol clock. The early/late-gate loops depend on symbol transitions to generate the error signals. Hence, they are prone to drifting from the correct symbol timing when the received signal contains a run of repeated symbols. This problem is reduced by having better-balanced integrators or by using a tau-dither loop, but both of these measures add significantly to the complexity of the synchronizers.
Under certain conditions, such as when the symbol clock is derived from a frame clock or a spreading code chip clock, a relatively slow (requiring several symbol periods) measure of the symbol quality is adequate for providing the feedback to the symbol clock. A system built from simple circuit elements to provide this measure would be a valuable tool in the design of communications receivers.
Such a system could also be used to configure a receiver with an appropriate timing for its symbol clock. If a receiver derives its symbol clock from another clock that has the same frequency but has a phase offset from the symbol transitions, then this system for evaluating the symbol clock would provide a simple means for measuring the phase offset at the end of the manufacturing process. The receiver can then be configured to use the measured value as an initial estimate of the offset during future operation.
SUMMARY OF THE INVENTION
One embodiment of the present invention contemplates a system and method for evaluating the quality of symbols in a communications receiver and for adjusting a symbol clock in the receiver so that the symbol quality is maximized. The invention presents a symbol quality detector, comprised in the receiver, that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are elements of a QPSK or DQPSK symbol constellation with additive noise, where all symbol constellation points {X
n
} can be described in polar coordinates as as (r, n&pgr;/2) with n=0, 1, 2, 3. Alternatively, the constellation points {X
n
} can be described in a 2-dimensional Cartesian plane as:
{X
n
}={(0,A), (A,0), (−A,0), (0,−A)}.
The projection of a given symbol X
n
along the ordinate I is a vector labeled i, and the projection along the abscissa Q is a vector labeled q. The i and q vectors form a 2-dimensional orthonormal vector basis when the amplitude A is appropriately normalized. The projections of the received symbols on the ordinate and abscissa are referred to as the I and Q components of the received symbol, respectively, or more simply, as I and Q. The symbol-quality detector comprises inputs that receive I and Q, and a logic block that generates the symbol-quality signal by constructing the quantity ||I|−|Q||. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation; it decreases if the detected symbols are rotated away from these constellation points. In a preferred embodiment of the invention, the symbol-quality detector comprises a latch that permits updates of the symbol-quality signal only during receive cycles, in which the receiver receives data.
The invention further contemplates an arrangement of elements in the logic-block of the symbol-quality detector. In this embodiment, the logic block comprises magnitude detectors that calculate the magnitudes of the I and Q components, an adder that adds the magnitude of the I component with the compliment of the magnitude Q component, thereby generating the difference |I|−|Q|, and another magnitude detector that operates on this difference to generate the quantity ||I|−|Q||.
Still further, the present invention comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock. Since a poor synchronization will cause the detected symbols to deviate from the expected constellation points, the symbol-quality signal is used in the receiver to measure the synchronization of the symbol clock with the symbol transitions in the received signal. This measure is preferably used to shift a phase of the symbol clock to refine its synchronization with the received symbols.
A second embodiment of the present invention contemplates a method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. In this embodiment of the invention, the receiver recovers from the received signal a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The method determines an optimal delay value by which the symbol clock should be shifted from the recovered timing so that the symbol clock is in phase with the symbol transitions. The method uses the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.


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Sklar, “Digital Communications: Fundamentals and Applications,” P T R Prentice Hall, Englewood Cliffs, New Jersey, 1988, pp. 453-460.

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