Pulse or digital communications – Systems using alternating or pulsating current
Reexamination Certificate
2006-07-11
2006-07-11
Tse, Young T. (Department: 2637)
Pulse or digital communications
Systems using alternating or pulsating current
C375S258000
Reexamination Certificate
active
07075996
ABSTRACT:
The present invention provides a chipset for transferring data through an electromagnetically coupled bus system. The chipset includes a modulator, a matching circuit and a demodulator. The modulator modifies a clock to encode multiple bits in a complementary pair of symbols. The matching circuit modifies the clock signal to generate a complementary pair of reference signals that is transmitted with the complementary symbol pair, and the demodulator decodes a second set of bits from selected properties of a complementary pair of transferred symbols.
REFERENCES:
patent: 3516065 (1970-06-01), Bolt et al.
patent: 3619504 (1971-11-01), De Veer Olney et al.
patent: 3764941 (1973-10-01), Nick
patent: 3786418 (1974-01-01), Nick
patent: 3835252 (1974-09-01), Ananiades et al.
patent: 4641322 (1987-02-01), Hasegawa
patent: 4825450 (1989-04-01), Herzog
patent: 4904879 (1990-02-01), Rudy, Jr. et al.
patent: 5179438 (1993-01-01), Morimoto
patent: 5365205 (1994-11-01), Wong
patent: 5621913 (1997-04-01), Tuttle et al.
patent: 5629838 (1997-05-01), Knight et al.
patent: 5638402 (1997-06-01), Osaka et al.
patent: 5867535 (1999-02-01), Phillips et al.
patent: 6005895 (1999-12-01), Perino et al.
patent: 6016086 (2000-01-01), Williamson et al.
patent: 6084883 (2000-07-01), Norrell et al.
patent: 6088741 (2000-07-01), Murata
patent: 6091739 (2000-07-01), Simonovich et al.
patent: 6111476 (2000-08-01), Williamson
patent: 6167132 (2000-12-01), Krone et al.
patent: 6246729 (2001-06-01), Richardson
patent: 6262998 (2001-07-01), Hogeboom
patent: 6446152 (2002-09-01), Song et al.
patent: 6449308 (2002-09-01), Knight, Jr. et al.
patent: 6496886 (2002-12-01), Osaka et al.
patent: 6498512 (2002-12-01), Simon et al.
patent: 6546055 (2003-04-01), Schmidl et al.
patent: 15 74 593 (1971-07-01), None
patent: 0 282 101 (1988-09-01), None
patent: 0 447 001 (1991-09-01), None
patent: WO 00/72163 (2000-11-01), None
Ramin Farjad-Rad et al., “A 0.3-μm CMOS 9-Gb/s 4-PAM Serial Link Transceiver”, IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 757-764.
Chih-Kong Ken Yang et al., “A 0.5μm CMOS 4.0 Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 713-722.
Hideki Osaka, “XTL Evaluation System, Evaluation Memory Sub-System: chip (HS-TEG:High Speed Test Engineering Group) and DIMM”, Intel-Hitachi, SDL601-XTL-0-073 DMX-005, Sep. 15, 2000, pp. 14 total.
Hideki Osaka, “High Performance Memory Interface for DDR-SDRAM II: XTL (Crosstalk Transfer Logic”, Intel-Hitachi, SDL601-XTL-0-074 DMX-006, Sep. 15, 2000, pp. 20 total.
Amirtharajah Rajeevan
Knight, Jr. Thomas F.
Marketkar Nandu J.
Simon Thomas D.
Ahn Sam K.
Metzger Erik M.
Tse Young T.
LandOfFree
Symbol-based signaling device for an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Symbol-based signaling device for an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Symbol-based signaling device for an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3553592