Sychronous semiconductor memory device with burst address counte

Details Sychronous semiconductor memory device with burst address counte Sychronous semiconductor memory device with burst address counte

1998-12-21

2000-01-04

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Counting

365233, 36523002, 36523006, 36523008, G11C 804

Patent

active

060117516

ABSTRACT:
A burst address counter comprising first to fourth decoder circuits for decoding address signals, first to fourth multiplexer circuits having first to third input terminals to receive the decoded address signals output from the first to fourth decoder circuits from the first input terminals, respectively, and selectively output one of input signals input to the first to third input terminals, first to fourth register circuits for storing output signals representing a burst address and output from the first to fourth multiplexer circuits, respectively, a first interconnection used in linear and interleave modes of single data rate scheme and connected to input the output signal stored in the first register circuit to the second input terminal of the fourth multiplexer circuit and the output signals stored in the second to fourth register circuits to the second input terminals of the first to third multiplexer circuits, respectively, and a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals stored in the first to third register circuits to the third input terminals of the second to fourth multiplexer circuits, respectively, and the output signal stored in the fourth register circuit to the third input terminal of the first multiplexer circuit.

REFERENCES:
patent: 5243576 (1993-09-01), Ishikawa

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