Sychronize processing circuit for multiscan display devices

Details Sychronize processing circuit for multiscan display devices Sychronize processing circuit for multiscan display devices

1998-02-17

2001-01-09

Hsia, Sherrie (Department: 2714)

Television

Synchronization

Automatic phase or frequency control

C348S537000, C348S524000

Reexamination Certificate

active

06172711

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of synchronize processing circuits in color television sets, display devices for regenerating synchronizing signals in video signals, and the supply of synchronizing signals with desired phases and widths to circuit blocks within color television sets and display devices.
BACKGROUND OF THE INVENTION
FIG. 12
shows a configuration of a synchronize processing circuit in accordance with the prior art. The synchronize processing circuit comprises a pulse phase setting circuit
37
, a pulse width setting circuit
38
, an AFC circuit
3
, a deflection output circuit
4
, a pulse phase setting circuit
39
, a pulse width setting circuit
40
, and a controller
6
. Synchronizing signal
7
is received from an outside source. The operation of the synchronize processing circuit as configured above is explained below.
In
FIG. 12
, the synchronizing signal
7
input to the synchronize processing circuit from an outside source is supplied to an analog pulse generator
35
consisting of the pulse phase setting circuit
37
and the pulse width setting circuit
38
. The analog pulse generator
35
is generally configured with a monostable multivibrator, so that the phase and width of the output signal in accordance with a control signal
9
from the controller
6
.
FIGS. 13A
to
13
C show the operation of the analog pulse generator
35
configured with the monostable multivibrator. When the synchronizing signal
7
is supplied to the pulse phase setting circuit
37
, a charging waveform responsive to a time constant determined by constants of a resistance element and capacitance element connected to the monostable multivibrator is created as shown in FIG.
13
B. This charging waveform enables creation of a synchronizing signal shown in
FIG. 13C
which has a different phase from the synchronizing signal
7
shown in FIG.
13
A. The phase setting is controllable by the control signal
9
output from the controller based on the time constant determined by the resistance element and capacitance element connected to the monostable multivibrator. A synchronizing signal with a specific pulse width is settable by supplying the output of the pulse phase setting circuit
37
(created as above) to the pulse width setting circuit
38
also configured with the monostable multivibrator. As explained above, a synchronizing signal with desired phase and width can be created from the synchronizing signal
7
input from the outside source to a display device by the use of the analog pulse generator
35
(which comprises the pulse phase setting circuit
37
and the pulse width setting circuit
38
).
The AFC circuit
3
receives the output of the analog pulse generator as mentioned above. The AFC circuit
3
generates a synchronizing signal synchronized to the input synchronizing signal by controlling the oscillation frequency of an oscillator built in the AFC circuit
3
. The synchronizing signal is output to the deflection output circuit
4
. The synchronizing signal supplied from the deflection output circuit
4
to a deflection coil (not illustrated) is fed back to the AFC circuit
3
after its voltage is divided. This stabilizes the deflection output circuit
4
.
An analog pulse generator
36
which has the same configuration as the analog pulse generator
35
receives a synchronizing signal with the same phase as, and synchronized to, the deflection current frequency of the display device. The synchronizing signal is input to the AFC circuit
3
from the deflection output circuit
4
. Mis analog pulse generator
36
enables supply of the synchronizing signal with desired phase and width to each control circuit in the display device.
However, with the above configuration of the prior art, phase and signal width of the synchronizing signal supplied to control circuits are determined by the analog element. Accordingly, a stable signal may be difficult to achieve due to the effect of characteristics peculiar to analog elements such as deviation in constants and temperature characteristics.
Furthermore, in the configuration of the synchronize processing circuit of the prior art, range setting of the phase and width of the synchronizing signal output from the analog pulse generators
35
and
36
is determined by the analog element connected to the monostable multivibrator in the analog pulse generators
35
and
36
.
If this type of circuit is employed in a multiscan display device which displays video images from video signal sources with a range of scanning frequencies, a percentage of a range setting of the phase and width of the synchronizing signal in one scanning frequency period may differ according to the scanning frequency of a video signal source input to the display device.
For example, if a variable range of the time constant of the analog element connected to the monostable multivibrator which determines the phase of the synchronizing signal is 5 &mgr;sec, a phase setting range of the synchronizing signal when an external video signal source with the horizontal scanning frequency of 100 kHz is connected is:
5 &mgr;sec/({fraction (1/100)} kHz)=50%.
If the scanning frequency of the video signal source input from the outside source is 20 kHz,
5 &mgr;sec/({fraction (1/20)} kHz)=10%.
It is apparent that the phase setting range of the synchronizing signal is narrowed on the display device.
In addition, the control signal
9
output from the controller
6
is generally a digital signal with a specified resolving power. If the control signal
9
from the controller
6
is a digital signal line with 10-bit resolving power in the above example, phase setting accuracy in the synchronizing signal per bit is different by 5 times between the scanning frequencies of 100 kHz and 20 kHz of video signal sources input from the outside source. Consequently, phase adjustment accuracy in the prior art may differ with scanning frequencies of external video signal sources input to a display device.
SUMMARY OF THE INVENTION
A synchronize processing circuit for multiscan display devices is for displaying one type of video signal from multiple video signal sources with different scanning frequencies. A PLL circuit is for implementing synchronizing regeneration of a synchronizing signal in an input video signal having a specified scanning frequency and outputting a regeneration clock. A controller is for generating a control signal. A first pulse generator receives one of a synchronizing signal of the video signal and a dividing output signal from a divider built in the PLL circuit, the control signal, and the regeneration clock, and outputs a synchronizing signal having a desired phase and width. An AFC circuit is for outputting a synchronizing signal. A deflection output circuit receives the synchronizing signal output from the AFC circuit and feeds back a synchronizing signal with the same phase as the deflection current frequency to the AFC circuit. A second pulse generator which receives the synchronizing signal and control signal output from the deflection output circuit and outputs a synchronizing signal with a desired phase and width.

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