Switching system with time-stamped packet distribution input sta

Details Switching system with time-stamped packet distribution input sta Switching system with time-stamped packet distribution input sta

1992-01-08

1993-10-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04L 1256

Patent

active

052532518

ABSTRACT:
In a fast packet switching system, packet distributors are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributor. Packet switches are provided corresponding in number to the output terminals of each packet distributor. Each packet switch has input terminals corresponding in number to the packet distributors and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributors for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from its input terminals and delivering the packets to the associated output port in accordance with the examined timeslot numbers.

REFERENCES:
patent: 4864558 (1989-09-01), Imagawa et al.
patent: 4891803 (1990-01-01), Huang et al.
patent: 4899334 (1990-02-01), Shimizu
patent: 5020052 (1991-05-01), DePrycker et al.
patent: 5022025 (1991-06-01), Urushidni et al.
patent: 5127000 (1992-06-01), Henrion
H. Kuwahara et al., "A Shared Buffer Memory Switch for an ATM Exchange", (CH26565-9/89/0000-0118) IEEE, 1989 pp. 0118-0122.

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