Multiplex communications – Wide area network – Packet switching
Patent
1991-07-29
1993-12-28
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 16, 370 941, 371 81, H04J 302
Patent
active
052746330
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a system for switching between systems in an exchange system in which an ATM switch is duplexed.
An ATM (Asynchronous Transfer Mode) network, unlike a conventional STM (Synchronous Transfer Mode) network, exchanges and transmits information with information to be transmitted being entered into an information element of a given length which is referred to as a cell. The cell, as shown in FIG. 1, is composed of a header for identifying a virtual channel and information containing actual information.
The ATM switch performs routing within the switch on the basis of the contents of the header. Thus, the transfer time of a cell varies with the route. In a duplexed ATM switch as well, the transfer time of a cell varies with its internal state even if the same route is set.
FIG. 2 illustrates the system configuration of a conventional duplexed (redundant) system. ATM data from a transmission line 1 is entered into a transmission line interface 2. The transmission line interface 2 distributes signals to duplexed ATM switches 3 and 4 equally. In both of the duplexed ATM switches 3 and 4, the same routing is performed.
A transmission line interface 5 on the output side receives cells from one of the ATM switches 3 and 4 that is in the active state and sends them out onto a transmission line 6.
FIG. 3 illustrates an example of an arrangement of the ATM switch (n.times.m cross switch). In this Figure, the ATM switch is adapted to output a cell from one of n input highways to one of m output highways.
In FIG. 3, the ATM switch is comprised of buffers 7 each of which is placed at an individual one of intersections of the input highways and the output highways, multiplexing sections 8 and highway sources 9 each corresponding to a respective individual output highway. Each of the highway sources 9 is adapted to output a bit indicating whether or not data is present on a corresponding channel, and each of the multiplexers 8 is adapted to capture an empty channel and insert a cell to be switched into the channel.
FIG. 4 illustrates a conventional duplexed system in which ATM switches are connected in multistages. In the Figure, ATM switches (cross switches) are connected in three stages. One of the outputs of both of the multistage-connected switches is selected by a system selector and then output onto a transmission line.
With the duplexed system using ATM switches shown in FIG. 2, however, since the transfer times of cells differ from each other even if the same route is set in the ATM switches 3 and 4, if the receiving-side transmission line interface 5 makes system switching by means of selection of cells, drop-out of cells and overlap between cells will occur. Thus, there is a disadvantage that systems cannot be switched without affecting call processing.
As described in connection with FIG. 3, there are provided buffers 7 for contention control in the ATM switch. If, for example, the power supply of one of the systems is turned off for maintenance and turned on again at the termination of the maintenance, a difference will arise between this system and the other system which has continued its operation in respect of data storing states of the buffers in the switches. Thus, there is a problem that drop-out, overlap and overstripping of cells occur if the systems are switched as they are.
SUMMARY OF THE INVENTION
In view of the above problems of the prior art, it is the object of the present invention to provide a switching system for an ATM switch duplexed system which allows accurate switching to be made between ATM switches so that drop-out of cells and overlap between cells will not occur.
FIG. 5 is a functional block diagram of a first system switching system. The figure is a functional block diagram of a first system switching system adapted to insert into an ATM cell a bit indicating that a system is active or on standby and enter it into an exchange.
In FIG. 5, at the input side of the exchange, in block 10, an AI bit indicating that the system is
REFERENCES:
patent: 4228535 (1980-10-01), Workman et al.
patent: 5072440 (1991-12-01), Isono et al.
Globecom '84, Atlanta, Georgia, Nov. 26-29, 1984, vol. 1, IEEE, New York, "Packet Switching in N Log N Multistage Networks", pp. 114-120.
Globecom '88, Hollywood, Florida, Nov. 28-Dec. 1, 1988. IEEE, New York, "A Second Generation Prototype for Broadband Integrated Access and Packet Switching", H. E. Bussey et al., pp. 1266-1271.
Patent Abstracts of Japan, vol. 009, No. 147 (E-323), Jun. 21, 1985; & JP-A-60 027 256 (Hitachi Seisakusho K.K.) Feb. 12, 1985 *Abstract*.
Patent Abstracts of Japan, vol. 014 No. 079 (E-888), Feb. 14, 1990; & JP-A-1 292 936 (Hitachi) Nov. 27, 1989 *Abstract*.
Aso Yasuhiro
Kakuma Satoshi
Kato Yumiko
Miyake Hiroshi
Uchida Yoshihiro
Blum Russell
Fujitsu Limited
Olms Douglas W.
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