Switching regulator and LSI system

Details Switching regulator and LSI system Switching regulator and LSI system

2000-04-28

2002-08-06

Patel, Rajnikant D. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S283000, C363S070000, C327S391000

Reexamination Certificate

active

06429633

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a technique concerning a switching regulator, and more particularly, it relates to a technique to reduce switching noise.
BACKGROUND ART
Recently, portable electronic equipment such as a portable telephone and a notebook personal computer has been remarkably spread. With the spread of such equipment, a technique to reduce power consumption has become indispensable in the field of semiconductor technology. In order to suppress the power consumption of an LSI, it is effective to reduce the power-supply voltage of the LSI itself, and for this purpose, a highly efficient power-supply voltage converting circuit is necessary.
A switching regulator is known to have much higher efficiency than a linear regulator due to its operation principle, and various systems for a switching regulator have been studied and developed. In accordance with increase of the operation speed and decrease of the power consumption of an LSI, there are increasing demands for a switching regulator with higher efficiency and higher switching speed.
FIG. 18
is a diagram for showing a basic circuit configuration of a conventional switching regulator, that is, a synchronous rectifiable buck switched-mode power-supply (DC/DC converter). A DC power-supply
1
is a source for generating the output of this switching regulator, and is a target to be chopped. The DC power-supply
1
is connected, at its power-supply port, to the source terminal of an output switching transistor
2
constructed from a P-type MOS transistor, and is connected, at its GND port, to the source terminal of a rectifier switching transistor
3
constructed from an N-type MOS transistor.
FIG. 19
is a timing chart for showing the operation of the switching regulator of
FIG. 18. A
controller
5
compares an output voltage Vout with a reference voltage Vref, and controls on/off operations of the switching transistors
2
and
3
on the basis of the result of the comparison. A voltage comparator
4
compares the output voltage Vout with the reference voltage Vref, and a pulse generating circuit
6
outputs a pulse signal SC for controlling the on/off operations on the basis of the result of the comparison. The signal SC is supplied to gate driving buffers
8
and
9
of the switching transistors
2
and
3
. The drain voltage VD of each of the switching transistors
2
and
3
is chopped by the on/off operation of the switching transistor
2
or
3
and a diode
11
, and the chopped voltage is smoothed by a smoothing circuit
10
including an inductance device
12
and a capacitor
13
, so as to be output as the output voltage Vout. The conversion efficiency is defined as follows:
Conversion efficiency=(Output power)/(Input power)
Problems to be Solved by the Invention
In order to keep high conversion efficiency in the conventional switching regulator, it is necessary to optimize a switching size by decreasing the on-resistances of the switching transistors
2
and
3
as much as possible, or/and to decrease an AC loss by increasing a switching frequency so as to conduct rapid switching. There arises, however, a problem that the rapid switching causes large switching noise.
Specifically, there exists a so-called parasitic inductor
102
on a power-supply line as is shown in FIG.
18
. When the source-drain voltage VDS of the switching transistors
2
and
3
is large, abrupt current change caused by the switching operation leads to occurrence of di/dt noise derived from the parasitic inductor
102
. This noise fluctuates the power-supply voltage level in every switching operation, resulting in causing similar noise also in the output voltage Vout. As a result, L·di/dt switching noise derived from the parasitic inductor
102
of the power-supply line is unavoidably caused in the output voltage Vout.
In order to reduce such switching noise, for example, a capacity inserting resonant switching regulator is conventionally used. The resonant switching regulator conducts ZVC (zero voltage switching) by utilizing LC resonance. The resonant switching regulator, however, has a problem of a very complicated configuration of its control circuit and is difficult to timely control. Furthermore, this resonant switching regulator has another problem that as the output current is larger, the AC loss is larger, resulting in decreasing the conversion efficiency.
Disclosure of the Invention
An object of the invention is reducing switching noise of a switching regulator while keeping high conversion efficiency.
Specifically, the switching regulator of this invention comprises plural output switching transistors operated in a predetermined order in at least one of an on operation and an off operation thereof.
According to the invention, the plural output switching transistors are operated in the predetermined order in at least one of the on operation and the off operation thereof. As a result, abrupt current change can be suppressed in the switching operation. Accordingly, di/dt noise derived from a parasitic inductor can be reduced.
In the switching regulator, the plural output switching transistors are preferably turned on in a descending order of on-resistance in the on operation thereof, and the plural output switching transistors are preferably turned off in an ascending order of on-resistance in the off operation thereof.
In the switching regulator, the plural output switching transistors are preferably turned on in an ascending order of transistor width in the on operation thereof, and the plural output switching transistors are preferably turned off in a descending order of transistor width in the off operation thereof.
In the switching regulator, one of the plural output switching transistors that is turned on first preferably has a drain current value in a non-saturation region larger than a maximum load current value of the switching regulator.
Preferably, in the switching regulator, the plural output switching transistors are divided into plural groups, and in the on operation thereof, the plural output switching transistors are turned on by group in an ascending order of the number of output switching transistors belonging to each group, and in the off operation thereof, the plural output switching transistors are turned off by group in a descending order of the number of output switching transistors belonging to each group.
The switching regulator preferably further comprises plural driving circuits provided correspondingly to the plural output switching transistors each for operating a corresponding one of the output switching transistors in accordance with a driving signal thereof, and at least one of the plural driving circuits preferably includes an inverter for driving a gate of the corresponding one of the out put switching transistors in accordance with the driving signal; and a constant current source circuit for controlling a current flowing through the inverter to be constant.
The at least one of the plural driving circuits preferably includes a current controlling circuit for controlling, in accordance with a load current quantity of the switching regulator, an amplitude of the current flowing through the inverter controlled by the constant current source circuit. Also, the at least one of the plural driving circuits preferably includes a non-overlap circuit that receives the driving signal and supplies a signal to the inverter for preventing a P-type MOS transistor and an N-type MOS transistor included in the inverter from being in an on state at the same time.
In the switching regulator, one of the plural output switching transistors having a comparatively large size is preferably placed comparatively closer to I/O pads of an LSI including the switching regulator and another of the plural output switching transistors having a comparatively small size is preferably placed comparatively farther from the I/O pads of the LSI.
Furthermore, the switching regulator preferably further comprises a timing setting circuit provided correspondingly to at least one of the plural output switching t

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