Amplifiers – Modulator-demodulator-type amplifier
Reexamination Certificate
2003-05-08
2004-12-14
Mottola, Steven J. (Department: 2817)
Amplifiers
Modulator-demodulator-type amplifier
C330S251000, C330S297000
Reexamination Certificate
active
06831508
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a switching power amplifier and a switching control method for a switching power amplifier, and particularly to a switching power amplifier and a switching power control method for the switching power amplifier suitable for being applied to the purpose of minimizing the effects of the noise generated by the switching power supply on the power amplifier stage in the switching power amplifier having a switching supply unit as a power source.
BACKGROUND ART
Signal amplifiers that are usually referred to as “class D-operation amplifiers” are conventionally known as one type of power amplifier. A typical example of a class D-operation amplifier is shown in FIG.
7
A. In the illustrated power amplifier, an analog signal S
1
inputted into a signal input terminal
1
is subjected to pulse width modulation by a pulse width modulation amplifier
2
. This pulse width modulation amplifier
2
generates a PWM (pulse width modulation) signal S
2
, in which the changes in the signal level of the analog signal S
1
are expressed as changes in the pulse width direction, and also a PWM signal S
3
with a waveform that is in a phase inversion relationship with the PWM signal S
2
.
It should be noted that in the following explanation, the waveform of the PWM signal S
3
is in a phase inversion relationship with the waveform of the PWM signal S
2
, so that these signals have a complementary relationship whereby when one of the signal waveforms of the PWM signal S
2
and S
3
is positive, the signal waveform of the other signal is negative.
It is also conventionally known that the power efficiency of class D-operation amplifiers is high, but to further increase the power efficiency of a power amplifier as a whole, it is conceivable to use a switching power supply circuit as the power supply. In
FIG. 7A
, numeral
10
is a clock with a fixed cycle period t, so that the PWM signal S
2
and the PWM signal S
3
that are based on the changes in the signal level of the analog signal S
1
are respectively generated and outputted by the pulse width modulation amplifier
2
as signals that are repeatedly produced in periods of t. It should be noted that the signal phase relationship between the PWM signal S
2
and the PWM signal S
3
is as described above, so that the signals have complementary characteristics whereby the signal phase of the PWM signal S
2
is in an inverse relationship with the signal phase of the PWM signal S
3
.
A DC voltage that has been stabilized at a preset fixed output voltage is generated by the switching power supply unit
11
and a positive DC voltage is supplied from the positive DC power supply terminal +Vcc of the switching power supply unit
11
to the power switching circuit
3
. It should be noted that the negative DC power supply terminal of the switching power supply unit
11
is grounded via an earth terminal
12
. A class D-operation amplifier differs from the example amplifier shown in
FIG. 7A
, in that it is composed as an amplifier with a positive
egative power supply, −Vcc is also outputted, and a neutral point between +Vcc and −Vcc is grounded.
In the power switching circuit
3
, the source of a first N-channel power MOSFET
4
(referred to hereafter as the “first power FET
4
”) is connected to the drain of a second N-channel power MOSFET
5
(referred to hereafter as the “second power FET
5
”), with the drain of the first power FET
4
being connected to the positive DC power supply terminal +Vcc of the switching power supply unit
11
and the source of the second power FET
5
being connected to ground.
A circuit that is constructed in this way of the first power FET
4
and the second power FET
5
is normally referred to as a “half bridge circuit”. Also, as shown in
FIG. 7A
, a pre-driver
28
is used as a half bridge driver that drives a half bridge circuit with the above construction. As one example, the pre-driver HIB2001B (registered trademark) that is manufactured by Intersil Corporation as a motor pre-driver can be used as this pre-driver
28
.
Via this pre-driver
28
, the PWM signal S
2
is converted into a signal S
7
that can perform an ON/OFF driving of the first power FET
4
, and the PWM signal S
3
is converted into a signal S
8
that can perform an ON/OFF driving of the second power FET
5
. The first power FET
4
is driven by the signal S
7
and the second power is driven by the signal S
8
, so that the first power FET
4
and the second power FET
5
are alternately switched ON and OFF by the PWM signals S
7
and S
8
. A PWM signal S
4
that switches in accordance with changes in the pulse width direction of the PWM signals S
7
and S
8
is generated and is outputted from between a connecting point located between the source of the first power FET
4
and the drain of the second power FET
5
and the earth connection.
After the PWM signal S
4
passes through a high frequency band-blocking power filter unit (hereafter referred to as the LPF (low pass filter) unit)
6
composed of a coil
7
and a capacitor
8
, and then through a capacitor
13
for removing the DC component, an analog power signal S
5
that reflects the changes in the signal level of the analog signal S
1
within the band of audible frequencies is demodulated from the PWM power signal S
4
. The demodulated analog power signal S
5
is supplied to the speaker unit
9
, where the analog power signal S
5
is reproduced as an audio signal.
FIG. 7B
shows several one-sided PWM-modulated waveforms as representative examples of the PWM-modulated waveform of the PWM signal S
4
. It should be noted that the name “one-sided PWM-modulated waveform” is used since both end edges (shown as “K” in
FIG. 7B
) of the PWM-modulated waveforms are fixed by locking them at the cycle period t of the clock signal S
6
, and a movable edge (M), which is a falling edge of the PWM-modulated waveform generated between both end edges of a fixed PWM-modulated waveform, is position-modulated in accordance with the signal level of the analog signal S
1
. Such PWM modulated waveforms are continuously generated one after the other.
It should be noted that other examples of one-sided PWM-modulated waveforms are also known. Such PWM-modulated waveforms are continuously generated with both of the fixed end edges of the PWM-modulated waveforms that are locked at the cycle period t of the clock signal S
6
being falling edges, and the rising edge of the PWM-modulated waveform that is generated between the two fixed edges of the PWM-modulated waveform being position-modulated in accordance with changes in the signal level of the analog signal S
1
.
It should be noted that in the following explanation, the edges in the waveform of the PWM signal S
4
that are locked by the clock signal S
6
at the timing determined by the cycle period t of the clock signal S
6
are referred to as the “fixed edges” of the PWM signal S
4
. As examples, in parts
1
B,
2
B, and
3
B of
FIG. 7B
, the waveform edges illustrated using upward-pointing arrows correspond to these fixed edges. Also, in the waveform of the PWM signal S
4
, the edge whose position changes in accordance with the signal level of the analog signal S
1
is referred to as the “movable edge M”. As examples, the waveform edges of the PWM signal S
4
that are shown by horizontal-pointing arrows in parts
2
B, and
3
B of
FIG. 7B
, correspond to movable edges M.
In the following explanation, out of the fixed edges, the edge that precedes the movable edge M is referred to as the “starting edge”. In the example shown in
FIG. 7B
, out of the two fixed edges K of the PWM-modulated waveform, the former fixed edge K, which is locked by the first waveform edge in the waveform of the clock signal S
6
as shown by the upward-pointing arrow (see part
4
B in FIG.
7
B), is the starting edge.
In the present example of one-sided PWM-modulated waveforms, the signal waveform of the PWM power signal S
4
at a point when the signal level of the analog signal S
1
is zero becomes a PWM-signal waveform wi
Maioli Jay H.
Mottola Steven J.
Sony Corporation
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