Switching element substrate having additional capacity and...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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Details

C349S140000

Reexamination Certificate

active

06359665

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device including switching elements such as thin film transistors (TFT) on each picture element and relates to a manufacturing method thereof.
BACKGROUND OF THE INVENTION
The following describes an arrangement of a conventional liquid crystal display device in which a peripheral driving circuit is formed on one of paired substrates on reference to
FIGS. 16 through 18
.
FIG. 16
is a plan view showing a substrate on which a peripheral driving circuit is formed, and
FIG. 17
is a drawing showing a layout of one picture element. Moreover,
FIG. 18
is a cross-sectional view taken along line A—A in FIG.
17
.
As shown in
FIG. 16
, a gate driving circuit
32
, a source driving circuit
33
and a TFT array section
34
are formed on an insulating substrate
31
which is one of the substrates in the liquid crystal display device. As the insulating substrate
31
, a glass substrate, a quartz substrate or the like is used. The gate driving circuit
32
is composed of a shift register
32
a
and a buffer
32
b.
Moreover, the source driving circuit
33
is composed of a shift register
33
a,
a buffer
33
b
and analog switches
39
. The analog switches
39
sample video signals to be inputted from the outside to a video line
38
.
A plurality of parallel gate bus wirings
116
which are extended from the gate driving circuit
32
are wired on the TFT array section
34
. Moreover, a plurality of parallel source bus wirings
120
which are extended from the source driving circuit
33
wired on the TFT array section
34
so as to perpendicularly intersect to the gate bus wirings
116
. The analog switches
39
are connected respectively to the source bus wirings
120
. Moreover, additional capacity common wirings
114
are wired on the TFT array section
34
so as to be parallel with the gate bus wirings
116
. Rectangular domains which are surrounded respectively by two gate bus wirings
116
, two source bus wirings
120
and two additional capacity common wirings
114
are provided with thin film transistors (i.e. TFT)
35
, picture elements
36
and additional capacities
37
. The TFT
35
functions as a switching element which electrically connects the picture element
36
, the gate bus wiring
116
and the source bus wiring
120
. A gate electrode of the TFT
35
is connected to the gate bus wiring
116
, and a source electrode of the TFT
35
is connected to the source bus wiring
120
.
A drain electrode of the TFT
35
is connected to a picture element electrode of the picture element
36
. The picture element
36
is composed of the picture element electrode a counter electrode provided on a counter substrate which faces the insulating substrate
31
, and a liquid crystal layer sealed between the picture element electrode and the counter electrode. Moreover, the additional capacity common wiring
114
is connected to a electrode having the same electric potential as the counter electrode.
The following details the arrangement of the conventional TFT array section
34
in
FIG. 16
on reference to
FIGS. 17 and 18
. A polycrystal silicon thin film
111
which is used as an active layer of the TFT
35
is formed on the insulating substrate
31
so as to have a thickness of, for example, 40 nm-80 nm. Then, a gate insulating film
113
is formed so as to have a thickness of, for example, 80 nm-150 nm by the sputtering or CVD method.
Phosphorus ions (P

) with concentration of 1×10
15
(cm
−2
) are implanted into a section
110
(a shaded portion in
FIGS. 17 and 18
) of the polycrystal silicon thin film
111
where the additional capacity
37
will be formed.
A metal or polycrystal silicon layer with low resistance which is used as the gate bus wiring
116
and the additional capacity common wiring
114
are formed on the gate insulating film
113
, and it is patterned so as to have a predetermined shape. As a result, a gate electrode
116
a
and an additional capacity upper electrode
114
a
are formed.
Thereafter, in order to determine a conduction type of the TFT
35
, phosphorus ions (P
+
) with concentration of 1×10
15
(cm
−2
) are implanted from the upper section of a gate electrode
116
a,
and a portion under the gate electrode
116
a
of the polycrystal silicon thin film
111
is a channel section
112
of the TFT
35
.
A first inter-layer insulating film
115
is formed on the whole surface of the substrate
31
by using SiO
2
or SiN
X
, and contact holes
118
and
119
are provided. Then, the source bus wiring
120
and a piling electrode (drain electrode)
121
are formed in the contact holes
118
and
119
by using metal with low resistance such as Al.
In the same manner as the first inter-layer insulating film
115
, a second inter-layer insulating film
124
is formed on the whole surface of the substrate
31
by using SiO
2
or SiN
X
, and a contact hole
123
is formed. Then, a picture element electrode
125
is formed by using a transparent conductive film such as ITO. When Al is used for the source bus wiring
120
and the piling electrode
121
, for example, in order to bring the piling electrode
121
into ohmic contact with the picture element electrode
125
, a barrier metal
126
is formed in the contact hole
123
by using metal such as Ti, TiW, Mo, MoSi.
However, the above-mentioned conventional liquid crystal display device has the following problems.
(1) First Problem
In the above arrangement, since the first and second inter-layer insulating films
115
and
124
are made of inorganic materials, the film thickness is small, i.e. several hundred nm, and the dielectric constant becomes higher than a usual organic material. For this reason, the capacity between the additional capacity common wiring
114
and the other wiring (for example, the source bus wiring
120
) becomes large, the additional capacity common wiring
114
is easily influenced by the other wirings. Therefore, when inorganic materials are used for the inter-layer insulating films
115
and
124
, it is not preferable that the additional capacity section is formed so as to greatly overlap the other wirings.
In addition, when the picture element electrode
125
is arranged so as to overlap the gate bus wiring
116
or the TFT
35
on an area connected to the picture element
36
, capacity Cgd′ is generated between the picture element electrode
125
and the gate bus wiring
116
or the TFT
35
. When the TFT
35
is turned off, a voltage drop (&Dgr;V) of the picture element electrode
125
represented by the following equation occurs.
&Dgr;
V=&Dgr;Vg×
(
Cgd+Cgd′
)/(
Cgd+Cgd′+Cs+C
LC
)
(&Dgr;Vg: potential difference between on-state and off-state of the gate, Cgd: capacity between gate and drain of TFT, Cs: additional capacity, C
LC
: liquid crystal capacity)
Since a d.c. component is applied to the liquid crystal due to the voltage drop, it is required to apply a bias voltage, for example, to the counter electrode.
In addition, since the additional capacity section does not have a light transmitting characteristic, an aperture ratio is lowered due to the additional capacity section. Moreover, the additional capacity common wiring
114
is formed on the layer where the gate bus wiring
116
is formed, and the additional capacity common wiring
114
does not have the light transmitting characteristic. As a result, the aperture ratio is lowered.
(2) Second Problem
Since the first inter-layer insulating film
115
is made of a inorganic material with a thickness of several hundred nm, disconnection of the source bus wiring
120
occurs due to unevenness of surface in a section where the source bus wiring
120
and the gate bus wiring
116
cross each other.
(3) Third Problem
In the above arrangement, the additional capacity common wiring
114
is formed by using the same material as the gate bus wiring
116
, and the gate insulating film
113
just under the wiring
114
is used as a dielectric. Since the gate insulating fil

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