Telecommunications – Receiver or analog modulated signal frequency converter – Squelch
Patent
1997-07-07
1999-03-16
To, Doris H.
Telecommunications
Receiver or analog modulated signal frequency converter
Squelch
455212, 455221, H04B 110
Patent
active
058841512
DESCRIPTION:
BRIEF SUMMARY
The subject of the patent is a circuit arrangement for brief mute switching of the reproduction of an LF signal in a radio receiver, is generically defined by the preamble to claim 1.
BACKGROUND OF THE INVENTION
One such circuit arrangement is known from the earlier German Patent Application P 43 26 097 of the same inventor. This known circuit arrangement attains the object of making extremely brief, hardly perceptible interruptions, free of clicking noises, in the LF signal of the radio receiver in order to carry out additional control operations.
SUMMARY OF THE INVENTION
The object of the present invention was to further improve the transition to the mute-switched or re-activated state in terms of freedom from clicking noises upon an interruption and in terms of avoiding perceptibility of the interruptions themselves.
This object is attained according to the invention by the provisions recited in claim 1.
Advantageous features of the invention are defined by the characteristics of the dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Details of the invention will be described in conjunction with the drawing. To that end,
FIG. 1 shows the function circuit diagram of the novel circuit arrangement;
FIG. 2 shows an exemplary embodiment of the novel circuit arrangement;
FIG. 3 shows voltage courses between two reference points of the exemplary embodiment;
FIG. 4 shows the voltage course at the output of the exemplary embodiment during a blanking pulse.
DETAILED DESCRIPTION OF THE INVENTION
The low-frequency useful signal that is to be interrupted briefly is carried in FIG. 1 from an LF input 1 of the circuit arrangement via a coupling capacitor C.sub.2 to a controllable semiconductor system that forms an interrupter 2. The output of the interrupter 2, which is connected to ground, via a resistor R.sub.3, simultaneously forms the LF output 3 of the circuit arrangement.
The resistor R.sub.3 also defines the DC operating point of the interrupter 2.
Connected to the output of the interrupter 2, that is, to the high point of the resistor R.sub.3, is a current branch 4, which is supplied from one output of a reversing switch 6. The current branch 4 is located parallel to the control branch 5 of the interrupter 2, which is connected to the other output of the reversing switch 6. The input of the reversing switch 6 is connected to a constant current source 7, which is connected to the terminal for the supply voltage U.sub.B.
The position of the reversing switch 6 is determined by the charge state of the capacitor C.sub.1, which is connected to ground via a resistor R.sub.2 and to the terminal for the supply voltage U.sub.B via a resistor R.sub.1. At the terminal 8, via the resistor R.sub.10, the blanking pulse is supplied to the high point of the capacitor C.sub.1 and to the reversing switch 6. The position of the switch arm of the reversing switch 6 determines whether the current from the constant current source 7 flows via the control path 5 of the interrupter 2 and the resistor R.sub.3 or via the current branch 4 and in turn the resistor R.sub.3 to ground. In both cases, the same voltage drop occurs at the resistor R.sub.3, so that at the LF output 3 no difference can be found, regardless of whether the LF signal itself is precisely equal to zero, or the interrupter 2 is preventing the further conduction of the LF signal. Because the potential at the high point of the resistor R.sub.3 remains constant, there is no charge reversal of the coupling capacitor C.sub.2, either, upon the mute switching or the cancellation thereof.
Thus no voltage changes, which could be the cause of clicking noises in the circuit, not shown in detail, connected to the output 3 of the circuit arrangement occur in the circuit arrangement.
In the exemplary embodiment of the circuit arrangement shown in FIG. 2, two antiparallel-connected npn transistors T.sub.1 and T.sub.2 form the aforementioned interrupter 2. The base terminals of the transistors T.sub.l and T.sub.2, which are located in the control circuit 5 of the interrupt
Robert & Bosch GmbH
Striker Michael J.
To Doris H.
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