Switching DC-to-DC converter with discontinuous pulse...

Details Switching DC-to-DC converter with discontinuous pulse... Switching DC-to-DC converter with discontinuous pulse...

2000-12-14

2002-05-28

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S225000, C323S284000

Reexamination Certificate

active

06396252

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to switching DC-to-DC converters, and to switching controllers for use in such converters.
2. Description of the Related Art
One type of conventional switching power supply circuitry which employs voltage feedback to achieve output voltage regulation is the DC-to-DC converter of
FIG. 1
, which includes current mode switching controller chip
1
, and buck converter circuitry external to the controller chip. The buck converter circuitry of
FIG. 1
comprises NMOS transistor N
1
(which functions as a power switch), inductor L, current sense resistor R
sns
, capacitor C, and feedback resistor divider R
F1
and R
F2
, connected as shown. The
FIG. 1
circuit produces a regulated DC output voltage V
out
across load R
LOAD
, in response to input DC voltage V
in
.
Controller chip
1
implements a control signal channel which generates pulse width modulated power switch control signals (“PWM switch control” signals) for power switches N
1
and N
2
in response to a ramped voltage (V
osc
) and a train of set pulses (generated by oscillator and ramped voltage generation circuit
2
), a feedback signal (supplied from Node A to the inverting input of error amplifier
10
) indicative of the DC-to-DC converter's output potential, and a feedback signal indicative of current through sense resistor R
SNS
. One of the PWM switch control signals (asserted at the “Q” output of reset dominant latch
89
) controls the gate of power switch N
1
. The other PWM switch control signal (asserted at the output of AND gate
102
) controls the gate of power switch N
2
.
Typically, each PWM switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signals. Specifically, the feedback provided from sense resistor R
SNS
to current sense amp
11
of controller
1
is a ramped voltage which is compared (in comparator
106
) with a reference potential (100 mV in the specific implementation shown in FIG.
1
). The output of comparator
106
is provided to one input of AND gate
100
. The feedback signal indicative of the DC-to-DC converter output potential is asserted to the inverting input of error amplifier
10
, and the noninverting input of error amplifier
10
is at a reference potential V
REF
. The output of error amplifier
10
is compared (by comparator
8
) with the ramped voltage V
OSC
summed with the current feedback signal from current sense amp
11
, and the output of comparator
8
is provided to the other input of AND gate
100
. The output of AND gate
100
is a train of reset pulses which drive one input of OR gate
113
. The other input of gate
113
is driven by the output of skip comparator
114
(which compares the output of error amplifier
10
and threshold potential V
th
). The output of OR gate
113
is employed to reset the latch
89
. The described use of the voltage V
OSC
improves stability through a technique known as “ramp compensation.” The value of the output of current sense amplifier
11
depends on the current through sense resistor R
SNS
(and thus the current through inductor L).
Controller chip
1
includes oscillator and ramped voltage generation circuit
2
, comparators
8
,
106
,
107
, and
114
, reset dominant latch
89
(having a “set” terminal coupled to receive the “set” pulse train from circuit
2
, a “reset” terminal coupled to the output of OR gate
113
, an output coupled to the gate of switch N
1
and to the “set” terminal of latch
91
, and an inverted output coupled to one input of AND gate
102
), latch
91
(having a “reset” terminal coupled to the output of comparator
107
and an output coupled to the other input of AND gate
102
), error amplifier
10
(having an inverting input coupled to Node A and a non-inverting input maintained at reference potential V
ref
), current sense amplifier
11
(having a non-inverting input coupled to the node between inductor L and resistor R
SNS
, an inverting input coupled to the buck converter circuitry's output node, and an output coupled to an input of comparator
106
and to summing node B). The other input of comparator
106
is maintained at a reference potential (which is 100 mV above ground in an implementation of the
FIG. 1
circuit, as indicated in FIG.
1
).
Reference potential V
ref
(asserted to the noninverting input of error amplifier
10
) is typically set by control bits and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V
out
, resistors R
F1
and R
F2
with the appropriate resistance ratio R
F1
/R
F2
are coupled to Node A.
Oscillator
2
asserts a clock pulse train (having fixed frequency and waveform as indicated) to latch
89
, and as long as the reset input to latch
89
is low, each positive-going leading edge of this pulse train sets latch
89
. Each time latch
89
is set, the potential asserted by latch
89
(the Q output of latch
89
) to the gate of transistor N
1
causes transistor N
1
to turn on. Although transistor N
1
turns on at times in phase with the periodic clock pulse train, it turns off at times (determined by the feedback signals, reference potential V
ref
and the compensating ramp) that have arbitrary phase relative to the pulses of the periodic clock pulse train asserted to latch
89
by oscillator
2
.
Each time latch
89
is set, the output of latch
89
sets latch
91
, but since the inverted output of latch
89
goes low, the output of AND gate
102
goes low (thus preventing transistor N
2
from turning on). After latch
89
has been set and before latch
89
is reset (while transistor N
1
is on), transistor N
2
remains off since the inverted output of latch
89
is low, forcing the output of AND gate
102
low. Then, in response to each reset of latch
89
, the inverted output of latch
89
goes high, thus forcing the output of AND gate
102
high and turning on transistor N
2
. After N
2
has been turned on (and N
1
has been turned off), the output of comparator
107
goes high (to reset latch
91
and turn off transistor N
2
) when the current I
IND
through inductor L falls to zero. This sequence repeats during normal (continuous mode) operation of the
FIG. 1
circuit (for as long as the output of comparator
106
remains high). During continuous mode operation of
FIG. 1
, the output of comparator
106
is high (a logical “one”), so that the reset times of latch
89
are determined by the output of comparator
8
(latch
89
is reset each time V
OSC
rises above the output of error amplifier
10
).
When the current I
IND
through inductor L falls below a threshold value (e.g., under light load conditions), the output of current sense amplifier
11
drops below the 100 mV threshold which causes the output of comparator
106
to go low. If this occurs, latch
89
cannot be reset until the output of amplifier
11
rises back above 100 mV. Transistor N
1
remains on, until the outputs of both comparator
106
and comparator
8
are high. Under light load conditions, this causes V
out
to rise and the output voltage of error amplifier
10
to fall. When the output voltage of error amplifier
10
(at node B) falls below V
th
, comparator
114
's output is held high, which drives the output of OR gate
113
high. This forces a constant high signal at the reset input of latch
89
, and prevents latch
89
from setting. In this way, the converter is forced to operate in a pulse skipping mode (in which it skips pulses). In the pulse skipping mode, both transistors N
1
and N
2
remain off (for two or more cycles of V
osc
) until latch
89
reset is released (i.e., until the output of OR gate goes low).
Upon entry into the pulse skipping mode (sometimes referred to as the “skip mode”), the reset input of latch
89
is held high by OR gate
113
(which forces the latch
89
to be reset), N
1
is forced off by latch
89
, and N
2
turns off and remains off once the inductor current I

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