Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-08-30
2001-06-12
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06246222
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to switching DC-to-DC converters having multiple power channels (either simple-paralleled or interleaved-paralleled) and multiple control signal channels, in which the duty cycle of each power channel is controlled by one of the control signal channels. Specifically, the invention employs rotation of a set of control signal channels (relative to a set of power channels) to reduce the differences between the time-averaged currents through the individual power channels.
2. Description of the Related Art
One type of conventional switching power supply circuitry which employs voltage mode control to achieve output voltage regulation is a DC-to-DC converter including a voltage mode switching controller chip, and circuitry external to the controller chip which defines multiple, paralleled power channels. The controller chip includes multiple control signal channels (one for each power channel), each control signal channel generating a pulse width modulated power switch control signal (“PWM switch control” signal) in response to a ramped voltage and a feedback signal indicative of the DC-to-DC converter's output potential. Typically, each PWM switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signal. Typically, the ramped voltage signals for all the channels increase periodically (with the same period for all channels) at a fixed ramp rate, and their waveforms are identical (to the extent possible and practical), except that each may have a different phase than the others. In interleaved PWM DC-to-DC converters, the ramped voltage signals and PWM switch control signals are out of phase with respect to each other. In non-interleaved PWM DC-to-DC converters having multiple channels, the ramped voltage signals and PWM switch control signals are in phase with respect to each other.
Each PWM switch control signal controls the power switch of a different one of the parallel power channels. For example, in PWM DC-to-DC converters, multiple PWM switch control signals are generated (in parallel) by providing multiple ramped voltages in parallel to comparator circuitry. Typically, it is desired that the PWM switch control signals all have the same duty cycle. Often, the PWM switch control signals are generated in a voltage mode switching controller chip, and asserted to external power switch circuitry (comprising multiple power switches) to cause the latter circuitry to determine the amplitude of the DC output voltage of the DC-to-DC converter. An advantage of providing multiple channels (each channel including a power switch) rather than a single channel is that use of multiple channels allows the DC-to-DC converter to be implemented with smaller power stage inductors, smaller input filter inductors, and smaller output capacitors, thus providing an overall improved step-load transient response and reduced physical size.
However, when implementing a multi-channel switching controller (especially when implementing it as an integrated circuit or part of an integrated circuit), process and temperature variations typically cause variations in the characteristics (e.g., maximum amplitude) of the ramped voltages generated in the individual control signal channels. Such variations typically cause or contribute to undesired variation from power channel to power channel in the time-averaged duty cycle of each power switch, and in the time-averaged current drawn from each power channel. This problem is sometimes referred to as “current hogging” by one or more power channels, or as the “hot channel” problem. When implementing a multi-channel DC-to-DC converter, a variety of factors typically contribute to the hot channel problem, including mismatches among the external power switches or other elements of the power channel circuitry external to the controller, as well as variations (from control signal channel to control signal channel) in implementation of the controller.
When implementing a multi-channel DC-to-DC converter, it is desirable to reduce or eliminate the hot channel problem, thus reducing mismatches causing any of the power channels from drawing significantly time-averaged current than any of the other power channels. Preferably, the converter is implemented so that all the power channels draw at least approximately the same time-averaged current.
FIG. 1
is a simplified circuit diagram of a conventional DC-to-DC converter which employs feedback of a type known as voltage-mode feedback which exhibits the “hot” channel problem in DC-to-DC converters having multiple (parallel) power channels. Specifically, mismatches in the slopes of ramped voltage V
osc
output from oscillator
2
for each channel of controller chip
1
, can result in mismatches in the current conducted through the inductor L, switch N
1
and diode D for each channel of the circuit. The degree of mismatch depends on the ramp rate of voltage V
osc
, the particular implementation of oscillator
2
and comparator
8
, as well as other circuitry within and external to controller chip
1
. Thus, in a multi-channel implementation of the
FIG. 1
circuit including comparators (such as comparator
8
) and circuitry for generating ramped voltages (such as voltage V
osc
) within each control signal channel, differences in V
osc
, inductor value, switch resistance and diode forward voltage can cause the “hot” channel problem by inducing variations (from power channel to power channel) in the time-averaged duty cycles of the power switches.
The
FIG. 1
circuit includes voltage mode switching controller
1
(implemented as an integrated circuit) and buck converter circuitry external to controller chip
1
. The buck converter circuitry comprises NMOS transistor N
1
(which functions as a power switch), inductor L, Schottky diode D, capacitor C
out
feedback resistor divider R
F1
and R
F2
, compensation resistor R
c
, and compensation capacitor C
c
, connected as shown. The
FIG. 1
circuit produces a regulated DC output voltage V
out
across load R
o
, in response to input DC voltage V
in
.
Controller chip
1
includes oscillator
2
(having a first output and a second output), comparator
8
, driver
6
which produces an output potential V
DR
at pad
12
(to which the gate of switch N
1
is coupled), latch
4
(having “set” terminal coupled to oscillator
2
, “reset” terminal coupled to the output of comparator
8
(having a first input coupled to the second output of oscillator
2
and a second input coupled to pad
13
and the output of error amplifier
10
, and an output coupled to the input of driver
6
), error amplifier
10
(having a non-inverting input maintained at reference potential V
ref
), digital-to-analog conversion circuit
10
A (which maintains the noninverting input of amplifier
10
at analog reference potential V
ref
, in response to digital control bits VIDCODE which determine the reference potential V
ref
and which are received from an external source at one or more pads
16
).
Pad
13
of controller chip
1
is at potential V
c
, which is determined by the output of error amplifier
10
(in turn determined by the difference between the instantaneous potential at Node A and the reference potential V
ref
) and the values of external resistor R
c
and capacitor C
c
, connected to pad
13
as shown. Reference potential V
ref
is set in response to bits VIDCODE and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V
out
, resistors R
F1
and R
F2
with the appropriate resistance ratio R
F1
/R
F2
are employed.
Oscillator
2
asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading edge of this pulse train sets latch
4
. Each time latch
4
is set, the potential V
DR
asserted by driver
6
to the gate of transistor N
1
causes transistor N
1
to turn on, which
Nilles Jeff L.
Phillips Darryl Byron
Berhane Adolf Deneke
Girard & Equitz LLP
National Semiconductor Corporation
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