Switching DAC pulse encoding circuit

Details Switching DAC pulse encoding circuit Switching DAC pulse encoding circuit

2003-02-25

2004-08-17

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06778116

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a digital-to-analog converter (DAC) and, more particularly, to a DAC that switches current from a current source to two separate switches during a single data clock cycle to reduce or eliminate transient non-linearity.
2. Discussion of the Related Art
Cellular telephone base stations employ RF transceivers for processing cellular telephone signals. The transceiver processing circuitry typically employs digital signal processing to demodulate and decode the receive signal, and encode and modulate the transmit signal. Because the transmit and receive signals are analog signals, the transceiver circuitry employs analog-to-digital converters (ADC) and digital-to-analog converters (DAC) to convert the signals from the analog domain to the digital domain and the digital domain to the analog domain to provide for digital signal processing. In some designs, an ADC may include one or more DACs as part of the conversion circuit.
In this application, it is typically necessary to provide extremely high accuracy and high resolution digital conversion, for example, on the order of twelve to sixteen bits. One data conversion scheme that requires high accuracy and high resolution is a delta sigma ADC or DAC. A delta sigma DAC is a circuit that employs over-sampling and quantization noise shaping to provide high resolution and high accuracy for a low resolution quantizer.
In some applications, such as in a delta sigma ADC and at the output of a transmitter, a DAC that exhibits excellent static and transient linearity is required. Transient non-linearity results from differences in the switching characteristics of the DAC depending on the incoming sequence of digital bits. For example, in a one bit DAC, the transition of the output voltage signal of the DAC representing a zero bit to the output voltage signal of the DAC representing a one bit (rise time) is different than the transition of the output voltage signal from a one bit to a zero bit (fall time). This data dependence is a source of transient non-linearity. A DAC with poor transient linearity will produce distortions significantly affecting its performance. This distortion typically manifests itself as inter-symbol interference (ISI) where the DAC output waveform for a particular clock period is a function of not only the sequence of digital bits applied to the DAC for that clock period, but also for the digital signal applied for a preceding clock period.
U.S. Pat. No. 6,061,010, titled Dual Return-to-Zero Pulse Encoding in a DAC Output Stage, issued May 9, 2000 to Adams et al., discloses a DAC that attempts to correct waveform distortions by employing a return-to-zero (RTZ) technique that masks DAC switching transitions and causes each bit time to contain both a rising edge and a falling edge. The '010 RTZ circuit operates by outputting an analog signal representing the digital input signal during the first half of a signal clock period, and outputting zero, or some reference level, during the second half of the clock period. The digital input signal changes states when the RTZ circuit is outputting a zero, so transient nonlinearity is masked.
FIG. 1
is a schematic block diagram of a DAC
10
showing the RTZ technique of the '010 patent. The digital data stream is applied to a first RTZ circuit
12
and a delay device
14
. The delay device
14
delays the data stream by one-half of a system clock signal, and applies the delayed digital data stream to a second RTZ circuit
16
. Therefore, the RTZ circuit
16
receives the same digital data stream as the RTZ circuit
12
, only delayed by one half of a clock period. A current signal from current sources
18
and
20
are also applied to the RTZ circuits
12
and
16
, respectively. The system clock signal is applied to the RTZ circuit
12
and an inverted system clock signal is applied to the RTZ circuit
16
. The analog current outputs of the RTZ circuits
12
and
16
are applied to a current summer
22
that sums the analog signals together to provide the desired analog output value over the complete clock period. Thus, for the positive part of the clock signal, the RTZ circuit
12
outputs the representative zero bit or one bit voltage level for that bit, and during the zero part of the clock signal, the RTZ circuit
16
outputs the same current level for that data bit.
FIG. 6
of the '010 patent shows a more detailed schematic diagram of the block diagram shown in
FIG. 1
above. As is apparent from a review of this figure, each of the two RTZ circuits includes a separate current source. The RTZ circuits include a differential pair of field effect transistors (FETs), where one of the FETs conducts for a one bit and the other FET conducts for a zero bit. Another FET in each RTZ circuit is caused to conduct for the part of the clock period where the other RTZ circuit is operational to direct the current signal away from the output. Particularly, the current source for the RTZ circuit that is not providing the output is coupled to a “throw-away point” when the other RTZ circuit is providing the output. The summed outputs from the RTZ circuits
12
and
16
are provided as differential outputs I
out+
and I
out−
.
The DAC disclosed in the '010 patent is effective in reducing transient non-linearity caused by transitions in the different voltage or current output levels of the DAC. However, because one of the current sources in the DAC is throwing its current signal away, this approach is inefficient. This results in a significant limitation in a DAC that must supply significant output power, such as in transmitters. Ideally, timing jitter during the switching between the output from the RTZ circuit
12
to the output from the RTZ circuit
16
does not induce an error because their outputs are the same. However, the timing jitter of the individual RTZ circuit
12
or
16
does contribute because it may cause both RTZ circuits
12
and
16
to be on or off at the same time. Further, the use of two current sources adds to system hardware and complexity.
BRIEF SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a digital-to-analog converter (DAC) is disclosed that provides reduced transient non-linearity and system inefficiency than those DACs known in the art. The DAC is responsive to a digital signal having a sequence of data bits that is split into a first path and a second path. The first path is coupled to a first switch and the second path is coupled to a delay device. The delay device delays the digital signal by one-half of a system clock cycle, and then applies the delayed digital signal to a second switch. A third switch is responsive to the system clock and switches current from a current source alternately between the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch, and when the clock signal is negative, the current signal is applied to the second switch.
Depending on whether the digital signal is high or low (one bit or a zero bit), or some value in between, the first and second switches will switch the current signal to a positive output summer or a negative output summer. If the digital signal is transmitting a one bit, the first switch will output the current signal to the positive output summer during the first half of the clock signal period and the second switch will output the current signal to the positive summer during the second half of the clock signal period. Likewise, if the digital signal is transmitting a zero bit, the first switch will output the current signal to the negative summer during the first half of the clock signal period and the second switch will output the current signal to the negative summer during the second half of the clock signal period. Thus, the output of the DAC is a positive signal or a negative signal for the entire clock period.
Additional advantages and features of the present invention will become apparent from

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