Switching circuit in a phase locked loop (PLL) to minimize...

Details Switching circuit in a phase locked loop (PLL) to minimize... Switching circuit in a phase locked loop (PLL) to minimize...

2008-01-28

2009-12-29

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

C156S563000

Reexamination Certificate

active

07639070

ABSTRACT:
In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit.

REFERENCES:
patent: 6611176 (2003-08-01), Goldman
patent: 6650195 (2003-11-01), Brunn et al.
patent: 6774731 (2004-08-01), Magazzu et al.
patent: 2005/0218948 (2005-10-01), Zhu et al.

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