Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-22
2001-06-19
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189110, C326S080000
Reexamination Certificate
active
06249458
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electrically erasable programmable floating gate memory devices and, more particularly, the present invention relates to a switching circuitry for controlling the various voltages utilized to program/erase such floating gate memory devices.
DISCUSSION OF RELATED ART
Electrically erasable programmable floating gate memory devices, such as flash memory devices, typically include an array of floating gate memory cells and associated control circuitry. Each floating gate memory cell includes a floating gate structure (e.g., polysilicon) that is surrounded by an insulation material (e.g., silicon dioxide) and located over a channel extending between a source and drain region formed in a substrate. A control gate is typically located on the insulation material over the floating gate structure. Current between the source and drain is controlled by the programmed/erased state of the floating gate structure. This programmed/erased state is determined by the number of electrons stored (captured) in the floating gate structure. The floating gate structure is erased (i.e., injected with electrons until the floating gate structure stores a net negative charge) by applying a first set of voltages to the source, drain, and control gate. This net negative charge resists source-to-drain currents during read operations. Conversely, the floating gate structure is programmed (i.e., electrons are discharged until the floating gate structure has a net positive charge) by a first set of voltages to the source, drain, and control gate. This net positive charge facilitates source-to-drain currents during read operations.
The program/erase operations of floating gate memory devices require relatively high voltage differentials (i.e., relative to read operations) to inject electrons into or discharge electrons from the floating gate structures. These programming voltages are applied to the source, drain and control gates of each floating gate structure in a predetermined pattern in order to perform the desired program or erase operation. Some floating gate memory devices utilize operation voltage schemes that include both positive (i.e., above ground) and negative (i.e., below ground) voltages to reduce the stress on chip elements. In these cases, relatively large voltage differentials are created by applying a positive voltage to one terminal of the memory cell and a negative voltage to another terminal, thereby creating large voltage potentials without requiring very large positive voltages. For example, a program operation may require a voltage equal to −8.0 V (Volts) to be applied to the control gate of a memory cell, while a read operation may require a voltage equal to −2.0 V to be applied to the control gate of the memory cell. For this reason, it necessary to provide multiple negative voltages (e.g., −8 V and −2 V) to a common node (e.g., the negative supply rail of a floating gate memory cell driver circuit).
FIG. 11
is a schematic diagram of a conventional switching circuit
1100
used to selectively provide multiple negative voltages to a common node (e.g., the negative supply rail of wordline driver
1110
, which is used to apply voltages onto the control gate CG of a floating gate memory cell
1115
). Transistor T
1
has a source coupled to a first negative voltage V
N1
(e.g., −8 V), a control gate coupled to a first control voltage V
CG1
(e.g., either 0 V or 3 V), and a drain coupled to a common node. Transistor T
2
has a source coupled to a second negative voltage V
N2
(e.g., −2 V), a control gate coupled to a first control voltage V
CG2
(e.g., either 0 V or 3 V), and a drain coupled to the common node. To selectively apply the first negative voltage V
N1
to the common node (e.g., to program floating gate memory cell
115
), a positive voltage (e.g., 3.0 V) is applied to the control gate of transistor T
1
, and 0 V is applied to the control gate of transistor T
2
. A problem with this arrangement arises, however, because the voltage differential between the drain of transistor T
2
, which is coupled to the −8.0 V on the common node, and the −2.0 V applied to the source allows current to flow through transistor T
2
, thereby preventing the common node from reaching the full −8.0 V required to program floating gate memory cell
1115
.
What is needed is a circuit that transfers multiple negative voltages (e.g., both −2 V and −8 V) to a common node that overcomes the leakage current deficiency of conventional switching circuit
1100
.
SUMMARY OF THE INVENTION
The present invention provides an electrically erasable programmable floating gate memory device that addresses the problems discussed above.
In accordance with a first embodiment of the present invention, an electrically erasable programmable floating gate memory device includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative supply rail of a driver circuit). The switching circuit includes a first switch connected between a first negative voltage supply and the common node, and a second switch connected between a second voltage supply and the common node. Each of the first and second switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources, thereby preventing the less-negative voltage source from pulling up the common node when a more-negative voltage is applied to the common node.
In accordance with another embodiment of the present invention, a triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the first and second switches. Each triple P-well resistor includes a central P-well region formed in a deep N-well region that in turn is formed in a P-substrate (or outer P-well). The N-well region is biased by a system voltage source (e.g., Vcc) and the P-substrate is grounded, thereby reverse biasing the central P-well region to limit leakage current from the P-well region.
REFERENCES:
patent: 4694430 (1987-09-01), Roher
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 6049498 (2000-04-01), Chen
Ahrens Michael G.
Sheen Ben Y.
Shokouhi Farshid
Bever Patrick T.
Bever Hoffman & Harms LLP
Cartier Lois D.
Nguyen Tan T.
Xilinx , Inc.
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