Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-03-17
2004-06-08
Pham, Chi (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S473000, C370S474000
Reexamination Certificate
active
06747974
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switching apparatus and, more particularly to, a switching apparatus to be preferably applied, for example, to an ATM switching system that performs switching process both in the AAL2 layer and the ATM layer.
2. Description of Related Art
Conventionally, the ATM (Asynchronous Transfer Mode) switching system performs processing such as switching and/or transmission of all information in the unit of fixed-length data called cells. The cell comprises a 5-byte header and 48-byte payload.
On the other hand, in the field of communications services that employ several ATM switching techniques and particularly mobile communications systems, a feasibility study on a voice-coding system that makes it possible to compress a voice with high efficiency is being carried out.
For example, using the voice-coding system called ITU-T (International Telecommunications Union—Telecommunications Standardization Division), Recommendation G. 729 (CS-ACELP) makes it possible to compress a voice rate of 64 kbps to 8 kbps or less.
However, in this case, assuming the cell assemble delay time to be approximately 6 ms for a 64 kbps voice and in order to fully fill the payload portion of an ATM cell with a voice at a rate of 8 kbps, a delay of approximately 48 ms would occur, which corresponds to eight times the delay time.
The cell may be transmitted without fully filling the payload portion of the ATM cell with voice information in order to shorten the cell assembly delay time. This would shorten the cell assembly delay time but would cause the payload to have wasted regions, resulting in reduced efficiency.
In order to overcome these problems, the AAL2 layer specifications have been recommended based on the ITU Recommendation I.363.2 as a new AAL (ATM Adaptation Layer). A I.366.1 is also available as an associated recommendation, a specification provided to allow an information frame longer than a voice such as a data stream to be divided and carried on the AAL2.
Although the aforementioned problems are overcome by the application of the AAL2, switching in AAL2 connection units, that is, a switching function in CPS packet units is required in addition to the switching function in ATM cell units in the case of handling the AAL2 by the ATM switching system. A conventional switching system that is provided with such a switching function is described in Japanese Patent Kokai No. 11-74892.
The cell switching system comprises an input packet processing circuit (input port), which determines whether an input including packet, for example, an ATM cell, includes an included packet, for example, a CPS (Common Part Sublayer) packet, and which performs, for an including packet which includes said included packet, demultiplexing processing of said included packet, header processing for the header of said included packet, and mapping processing for mapping each respective demultiplexed included packet associated with a switching including packet for switching processing; a switch (for example, a cell switch) for performing switching processing of said switching including packet and a switching including packet which does not include said included packet; and an output packet processing circuit which determines whether a switching including packet which is switched and outputted from said switch includes an included packet and which performs, for a switching including packet which includes said included packet, demultiplexing processing of said included packet and re-mapping processing for mapping said demultiplexed included packet in an including packet that is different from a switching including packet.
This cell switching system has made it possible to handle both the ATM cell not including CPS packets (short packets) and the ATM cell including CPS packets without providing a special configuration to a cell switch for a conventional ATM cell.
The configuration of said cell switching system
10
is shown in FIG.
1
.
Referring to
FIG. 1
, the cell switching system
10
is provided, on the input side of an ATM switch
108
, with a plurality of input ATM cell processing circuits
100
(the first) through
101
(the nth); on the output side of an ATM switch
108
, with a plurality of output ATM cell processing circuits
120
(the first) through
115
(the nth).
In the foregoing, the ATM switch
108
is a typical ATM switch that is a component corresponding to said cell switch.
Since respective input ATM cell processing circuits have a common internal configuration, only the first input ATM cell processing circuit
100
coupled to the first input port is explained.
The input ATM cell processing circuit
100
(corresponding to said input packet processing circuit) comprises an input ATM cell header processing circuit
102
, an input ATM cell allocating circuit
103
, an input AAL2 processing circuit
104
, cell buffers
105
and
106
, and an input ATM cell multiplexing circuit
107
.
Said input ATM cell header processing circuit
102
is a circuit for attaching a switching tag to be used for processing in the switching system
10
to the head portion of an inputted ATM cell. For example,
FIG. 2A
shows said ATM cell before being attached with the tag, while
FIG. 2B
shows said ATM cell after being attached with the tag.
Referring to
FIG. 2A
, an ATM cell
231
comprises an ATM cell payload
232
and an ATM cell header
233
. In
FIG. 2B
, an in-switch ATM cell
241
comprises an in-switch ATM cell payload
242
, an in-switch ATM cell header
243
, and said switch tag
244
. The switch tag
244
comprises a CPS packet identifier that indicates whether the cell payload
232
of said ATM cell
231
includes a CPS packet.
Said input ATM cell allocating circuit
103
is a circuit that allocates in-switch ATM cells by referring to the CPS packet identifier of the switch tag
244
. In this allocation, the in-switch ATM cell that includes a CPS packet is allocated to the side of the input AAL2 processing circuit
104
, while the in-switch ATM cell that does not include a CPS packet is allocated to an input ATM cell buffer circuit
106
.
The input AAL2 processing circuit
104
is a circuit that performs processing of the AAL2 layer, that is, the terminating processing circuit of the AAL2 layer in accordance with the ITU-T Recommendation I.363.2. This terminating processing of the AAL2 layer performs the demultiplexing processing of individual. CPS packets and the mapping processing to the payload portion of the in-switch ATM cell.
The input AAL2 processing circuit
104
includes a CPS packet layer processing circuit
104
A, a CPS packet header processing circuit
104
B, and a CPS packet converting circuit
104
C, from the input side in that order.
The first CPS packet layer processing circuit
104
A is, among processing of the AAL2 layer, in charge of demultiplexing the CPS packets as well as providing the headers of the in-switch ATM cells that have undergone said demultiplexing to the subsequent CPS packet header processing circuit
104
B.
The CPS packet layer processing circuit
104
A refers to the CID (Channel ID), that is, a connection identifier at the AAL2 layer level included in the CPS packet header and performs header processing. This header processing converts, for example, said CID.
The last CPS packet converting circuit
104
C in the input AAL2 processing circuit
104
performs packing (mapping) CPS packets into the payload portion of the in-switch ATM cell. This mapping operation is to allow said ATM switch
108
to make it possible to execute the switching processing for CPS packets in the same manner as for typical ATM cells.
CPS packets
302
and
303
of an ATM cell
301
that are inputted into the input ATM cell header processing circuit
102
under the state as shown in
FIG. 3A
are inserted into separate payloads
311
and
321
of the in-switch ATM cell like an in-switch CPS packet
2
and an in-switch CPS packet
1
which are shown in
FIGS. 3B and 3C
, as a result of this mapping operation. The in-switch ATM cel
Do Nhat
Oki Electric Industry Co. Ltd.
Pham Chi
Sartori Michael A.
Venable LLP
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