Amplifiers – Modulator-demodulator-type amplifier
Reexamination Certificate
1999-09-27
2002-10-29
Mottola, Steven J. (Department: 2817)
Amplifiers
Modulator-demodulator-type amplifier
C330S20700P
Reexamination Certificate
active
06472933
ABSTRACT:
FIELD OF INVENTION
Invention relates to amplifier circuits, and more particularly to switching amplifier power switch.
BACKGROUND OF INVENTION
“Typical Class-D amplifier such as that of Texas Instrument (TI) Cass D Stereo Audio Power Amplifier described in TI TPA005D02 Class D Stereo Audio Power Amplifier Evaluation Module User's Guide comprises an analog input and an analog output. A simplified Class-D amplifier is illustrated in FIG.
1
. The amplifier constitutes two parts: the control circuit
20
and the H-bridge
30
. The control circuit
20
consists of a saw-tooth waveform generator
201
and a comparator
202
. The analog input
11
is compared with the saw-tooth waveform to produce a binary digital output
31
. The binary digital output is then used to control the ON/OFF of an output power stage such as an H-bridge circuit
30
. As shown in greater detail in
FIG. 2
, H-bridge circuit
30
comprises two pairs of switches, a first pair of switches: switch
102
(AH) and switch
104
(AL), and a second pair of switches: switch
106
(BH) and
108
(BL). Each pair of switches comprises a first switch (i.e., AH or BH) connected to a positive power supply
101
(VP) and a second switch (i.e., AL or BL) that is connected to a negative power supply
103
(VM) to thereby switch amplifier
20
between a positive and negative digital output state (i.e., equivalent to a digital “+1” output voltage and a “−1” output voltage) via a set of input switch control signals
105
,
107
,
109
, and
111
(VAH, VAL, VBH, and VBL, respectively). The output load
110
is connected to the output switches via the output nodes
112
(V+) and
114
(V−) as shown in FIG.
2
. During the “+1” state, the set of amplifier switch control signals
105
,
107
,
109
, and
111
controlling switches, AH, AL, BH, and BL are designed to connect node
112
(V+) to positive power supply (VP) and node
114
(V−) to negative power supply (VM). During the “−1” state, the set of amplifier switch control signals
105
,
107
,
109
, and
111
controlling switches, AH, AL, BH, and BL are designed to connect node
112
(V+) to negative power supply (VM) and node
114
(V−) to positive power supply (VP). For traditional Class-D amplifier, the output switches between “+1” and “−1” states alternatively depends on the control circuit
20
. Depending upon the nature of the input waveform, the switch-on time for the pull-up and pull-down transistors can be very narrow such that the pulse is shorter or comparable to the rise time or fall time of the power switches
105
,
107
,
109
,
111
. This correspondingly also results in distortion in the output circuit. In real implementations, special transistors (e.g., DMOS or JFET) are used in the H-bridge since they have much faster turn-on time that a standard MOS transistor. An apparent drawback for this type of Class-D amplifier is that while the control circuit
20
in
FIG. 1
can be implemented in CMOS, the H-bridge is typically outside the controller circuit. Since modern VLSI adapts CMOS as the dominant technology due to its advantage of lower cost and high integration capability. The integration level is not optimum and hence the cost is higher than a single integrated CMOS Class-D amplifier.”
Another prior solution, such as shown in U.S. Pat. No. 5,777,512 (“the '512 Patent”), includes a feedback loop to reduce the overall harmonic distortion of the H-bridge. In the '512 Patent, an analog sigma-delta modulator is used to produce the binary digital output, and the output of the amplifier is then fed back to the sigma-delta loop to reduce the distortion. Both the traditional saw-tooth and binary sigma-delta modulation provide poor power efficiency due to their frequent switching even when there are little or no input signals. Another problem is caused by the binary nature of the output state and finite turn-on resistance associated with the transistors of the H-bridge is that there will always be power consumed by these transistors regardless of the shape or amplitude of the input signal. As illustrated in
FIG. 2
, due to the binary nature of the output state, at any given time, either the transistor
102
and
108
are “ON” (+1 state), or
106
and
104
are “ON” (−1 state). In either case, there is a current path from positive supply
101
to negative power supply
103
. The power consumed by each transistor
102
,
104
,
106
, and
108
is the product of the current times the turn-on resistance associated with each transistor. Thus, because of these binary states, power consumption is always present even if there is no input signal to amplify.
“In U.S. Pat. No. 5,077,539 (“the '539 Patent), a ternary output switching amplifier is introduced. A major advantage of the ternary output switching amplifier is the higher power efficiency for small input signal. This efficiency is achieved by introducing the third state 0. In
FIG. 2
, when the amplifier outputs a 0 state, both output terminals
112
(V+) and
114
(V−) of output load
110
are short circuited to a supply voltage of a pre-determined polarity, i.e., the positive power supply voltage. Since both the output terminals have the same voltage, there is no current flow through the load and the transistors
102
,
104
,
106
, and
108
, hence the power consumption is zero during 0 state. If designed properly, for a small amplitude input signal, the output preferably will have many 0 states and the power consumption is then much smaller than the binary switching amplifiers described earlier. One possible implementation of ternary switching amplifier is disclosed in U.S. Pat. No. 5,617,058 (“the '058 Patent”), in which a pulse width logic is used to convert digital data into a ternary switching signal. While the ternary power switch amplifier can achieve higher power efficiency than binary power switch amplifiers, there is significant harmonic distortion caused by the error caused by the error voltages associated with the output transistors as explained below:”
As illustrated in
FIG. 5
, there are error voltages associated with the output nodes V+ and V− switching between the positive and negative supply voltages. The associated error voltages result from the finite rise and fall time as well as the settling time of the output transistors
102
,
104
,
106
, and
108
. The error voltages associated with these transistors are correspondingly denoted as V(AH), V(AL), V(BH) and V(BL). To simply the analysis, we assume that error occurs when the transistors change from “Off” (opened) to “ON” (closed). Since the turn-off time of a transistor is independent of the load and can be well controlled, it is typically much shorter than the turn-on time. Thus, the error associated with the turn-off time of a transistor is much shorter than that associated with the turn-on time of a transistor. We therefore neglect its effect in the following analysis. In the preferred typical implementation, the transistors
102
and
106
are of the same type (for example PMOS) and transistors
104
and
108
are of the same type (for example NMOS) and are operated under the same switching condition. Thus, V(AH)=V(BH), and V(AL)=V(BL). On the other hand, the pull-up transistors
102
and
106
, and the pull-down transistors
104
and
108
are typically of different type or switched under different conditions. Hence, these transistors are not matched, and consequently V(AL)≠V(AH) and V(BL)≠V(BH). Accordingly, due to this mismatch, the ternary switching sequence introduces substantial harmonic distortion at the output.
For example, consider the switching sequence shown in
FIG. 4
wherein the output switches between just the +1 state and the 0 state. At each occurrence of a 0 state, both nodes V+ and V− of load
110
are typically switched “HIGH” to supply VP (referring to FIG.
2
). As seen from
FIG. 4
, the positive end of the load (V+) always remain at VP, while the negati
Carr & Ferrell LLP
Mottola Steven J.
Waytech Investment Co. Ltd.
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