Switching algorithm for clock distribution function

Details Switching algorithm for clock distribution function Switching algorithm for clock distribution function

1998-07-21

2000-06-20

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 1A, 331 74, 327144, 327150, G06F 104

Patent

active

060782250

ABSTRACT:
An output clock signal is generated from a selected input clock signal using a phase-locked loop (PLL). The output clock signal is used to detect failures in the selected input clock signal. If a failure is detected, a backup input clock signal is used to generate the output clock signal. In one embodiment, a clock detector has a counter that is initialized based on the selected input clock signal and incremented based on the output clock signal. The clock detector detects a failure in the selected input clock signal if (1) the counter is reset too early or too late, as determined by the counter value, or (2) the signal level in the selected input clock signal does not change within a specified time period. Upon detection of a clock-signal failure, the clock detector switches to a backup input clock signal and, depending on the magnitude of the phase offset between the failed input clock signal and the backup input clock signal, temporarily changes the divisor value used by the PLL and applies a phase build-out sequence. The present invention is designed to achieve hitless or at least near hitless switching between timing functions.

REFERENCES:
patent: 5903748 (1999-05-01), McCollough et al.

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