Switched substrate bias for MOS-DRAM circuits

Details Switched substrate bias for MOS-DRAM circuits Switched substrate bias for MOS-DRAM circuits

1996-09-05

1997-12-30

Westin, Edward P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

326 33, 36518909, G05F 316, H03K 1716

Patent

active

057035229

ABSTRACT:
A semiconductor circuit or a MOS-DRAM wherein a converter is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converter includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

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"MT-CMOS: 1V High-Speed CMOS Digital Circuit Technology", by Shin'ichiro Mutoh et al., The Institute of Electronics, Information and Communication Engineers Spring Convention, 1994, C-627, 5-195.
"1V High-Speed Digital Circuit Technology with 0.5.mu.m Multi-Threshold CMOS", by Shin'ichiro Mutoh et al., Proc. IEEE ASIC Conference, 1993, pp. 186-189.
"Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's", by Takeshi Sakata et al., Symposium on VLSI Circuit Digest of Technical Papers, pp. 45-46.

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