Switched impedance comparator

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307362, 307530, 307279, H03K 5153, H03K 524

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active

048146420

ABSTRACT:
A high-speed synchronous comparator circuit, well suited for use in an analog to digital converter. The circuit is switched between acquisition and regeneration modes and includes an amplifier that is operated with positive feedback loop gain in both modes. In the acquisition mode, a relatively low impedance is connected between internal nodes of the amplifier, to improve acquisition speed and keep the positive feedback loop again less than unity. In regeneration mode, the low impedance is disconnected, resulting in a high positive feedback loop again and a desirably amplified output indicative of the polarity of the input differential signal, and the input signal is isolated from the latching nodes. The invention may be implemented in a variety of fabrication technologies, including gallium arsenide field-effect transistors, complementary metal-oxide semiconductor (CMOS) circuitry, and bipolar transistors.

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patent: 4253163 (1981-02-01), Komoriya et al.
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patent: 4264872 (1981-04-01), Suzuki
patent: 4511810 (1985-04-01), Yukawa
patent: 4542308 (1985-09-01), Winen
patent: 4602167 (1986-07-01), Yukawa
patent: 4629911 (1986-12-01), Bebernes et al.

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