Amplifiers – Combined with automatic amplifier disabling switch means
Reexamination Certificate
1999-07-26
2001-01-16
Mottola, Steven J. (Department: 2817)
Amplifiers
Combined with automatic amplifier disabling switch means
C330S100000
Reexamination Certificate
active
06175274
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to communications electronics and, more specifically, to low noise amplifiers used in communications downconverters.
BACKGROUND OF THE INVENTION
The sensitivity of a typical communications receiver (i.e., the ability of the receiver to recover information in the presence of noise) depends, in part, on the noise figure of the receiver. This (the noise figure) is the excess noise generated by the receiver and translated to its input, as compared to the thermal noise (expressed in decibels). The noise figure of the receiver depends strongly on the performance of a low noise amplifier found at the front of the receiver.
An example of such an amplifier
10
is shown in FIG.
1
. As shown, the low noise amplifier
10
includes a common-emitter gain stage that comprises an input capacitor
12
for receiving an RF signal, an inductor L
e
that provides emitter degeneration and helps set the input impedance R
IN
of the amplifier
10
, and a bipolar transistor
14
. In addition, the amplifier
10
may include a cascode stage for minimizing Miller capacitance and improving reverse isolation of the amplifier
10
. The cascode stage comprises an AC grounding capacitor
16
and another bipolar transistor
18
that together receive a bias voltage V
bias
, and a load element Z
C
that typically includes an inductor and resistor in parallel. The amplifier
10
may also include a bypass MOS transistor
20
that can bypass the common-emitter gain stage when the RF signal is strong.
It is desirable for the input impedance of the amplifier
10
to be 50&OHgr;, both in its “normal” or “high-gain” mode (i.e., when the bypass transistor
20
is off) and in its “bypass” or “low-gain” mode (i.e., when the bypass transistor
20
is on). In the normal mode, the input impedance R
IN
of the amplifier
10
is determined in accordance with:
R
IN
≈r
&pgr;
+&rgr;&bgr;L
e
(1)
where r
&pgr;
is the small-signal base-emitter input resistance looking into the base of the bipolar transistor
14
, &rgr; is the dominant pole associated with &bgr;, and &bgr; is the common-emitter current gain. The value of the inductor L
e
is selected from this equation.
There are several drawbacks to the design of this amplifier
10
. For example, the required gain for the single-stage amplifier
10
is significant. Also, the inductor L
e
and the inductor in the load element Z
C
are typically off-chip, which allows these inductors to couple to input pins and destabilize the amplifier
10
. Further, the amplifier
10
can be difficult to tune because the input impedance R
IN
, the input compression point, and the noise figure of the amplifier
10
are set by transistor geometry, inductor degeneration, and quiescent current, all of which are heavily interdependent. In addition, it is difficult to get the bypass mode input impedance, which is set by the MOS transistor
20
, to match the normal mode input impedance R
IN
, which is set as discussed above.
Accordingly, there is a need in the art for an improved low noise amplifier.
SUMMARY OF THE INVENTION
An inventive amplifier (e.g., a low noise amplifier) includes a first gain stage that receives an input signal (e.g., an RF signal) and, in response, generates an amplified signal in, for example, the high-gain mode of the amplifier and a low-gain signal in the bypass mode of the amplifier. In the high-gain mode, switching circuitry outputs the amplified signal, and a second gain stage generates an output signal in response. Also, in the high-gain mode shunt circuitry feeds the output signal back to the first gain stage, and in the bypass mode feeds the low-gain signal forward as the output signal.
This inventive amplifier has improved matching of its bypass mode input impedance and its high-gain mode input impedance, improved stability due to the feedback through the shunt circuitry in the normal mode, and improved reverse isolation due to the two stage amplifier design.
In a further embodiment, the amplifier described above is incorporated into a communications downconverter that also includes an image rejection filter and a mixer.
In another embodiment, an inventive low noise amplifier generates an output voltage from an RF signal. The amplifier includes a first gain stage having a bipolar transistor that receives the RF signal at its base and generates an amplified signal at its collector in the normal mode of the amplifier and a low-gain signal at its emitter in the bypass mode of the amplifier. Also, switching circuitry includes first and second bipolar transistors with their emitters coupled to the collector of the first gain stage bipolar transistor, and an inverter coupled to the bases of the first and second bipolar transistors that receives a bypass signal and, in response, switches on the second bipolar transistor and switches off the first bipolar transistor for common-emitter operation of the first gain stage in the normal mode, and switches off the second bipolar transistor and switches on the first bipolar transistor for emitter-follower operation of the first gain stage in the bypass mode. In addition, a second gain stage includes a bipolar transistor with its base coupled to the collector of the second bipolar transistor of the switching circuitry that receives the amplified signal and generates the output voltage at its collector in the normal mode. Further, shunt circuitry includes an impedance network coupled between the collector of the second gain stage bipolar transistor and the emitter of the first gain stage bipolar transistor that feeds the output voltage back to the first gain stage in the normal mode and couples directly the emitter voltage at the first gain stage to the output of the second gain stage in the bypass mode.
In still another embodiment, an input signal is amplified by first receiving the input signal with a first gain stage. Then, in the normal mode, the first gain stage is switched into common-emitter operation, an amplified signal is generated from the input signal using the first gain stage, an output signal is generated from the amplified signal using a second gain stage, and the output signal is fed back to the first gain stage through shunt circuitry. Also, in the bypass mode, the first gain stage is switched into emitter-follower operation, a low-gain signal is generated from the input signal using the first gain stage, and the output signal is generated from the low-gain signal using the shunt circuitry.
REFERENCES:
patent: 3304506 (1967-02-01), Weekes
patent: 3737798 (1973-06-01), Faraguet et al.
patent: 4563652 (1986-01-01), Hofer
patent: 5590412 (1996-12-01), Sawai et al.
patent: 5909643 (1999-06-01), Aihara
Mottola Steven J.
Nokia Mobile Phones Limited
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