Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-12-21
2003-06-17
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S056000, C361S058000, C361S091100, C361S111000, C361S118000, C361S119000
Reexamination Certificate
active
06580591
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit (IC) protection circuits, and more particularly to a switched electrostatic discharge (ESD) ring for ICs with multiple power inputs to improve ESD protection and pin isolation.
DESCRIPTION OF RELATED ART
ICs are subject to damage by ESD while they are being handled during testing, packing, shipping or assembly onto a printed circuit board (PCB). Static charge may build up on the IC package body, a human being or test/handling equipment and then discharge through one or more external pins of the IC thereby damaging the internal circuitry of the IC. Extra circuits are often added to the IC to mitigate this problem.
A simple known ESD network includes a first series of diodes each having their anodes connected to respective IC pins and their cathodes connected to the positive power (or voltage) supply pin. A second series of diodes are provided having their anodes connected to ground or the negative power pin and their cathodes connected to respective IC pins. It is noted that throughout this disclosure, reference to “negative” power pins, voltages, voltage rails, terminals or nodes with reference to power-related pins includes ground pins depending upon IC configuration (e.g., the negative power pins may be or otherwise include ground pins). Thus, each pin is coupled between the positive and negative power inputs via a pair of ESD diodes. A voltage clamp, such as a Zener diode or the like, is also coupled between the positive and negative supply pins. The voltage clamp draws current when the voltage across it exceeds its threshold voltage level. When the IC is mounted to a PCB and powered on, each of the ESD diodes are reversed biased as long as the voltages on the pins are between the supply voltage. An ESD pulse that would otherwise cause any pin to rise significantly above the positive voltage rail or below the negative voltage rail (or ground) forward biases a corresponding ESD diode to protect the internal circuitry. When the IC is isolated and not connected to a power supply, an ESD pulse applied between any two pins activates two or more corresponding ESD diodes and the voltage clamp so that current flows directly through the pins to protect the internal circuitry.
The simple ESD network just described provides good isolation between respective pins. Noise from the power supply or ground, however, couples to any one or more of the pins and to the rest of the circuit connected to these pins. In this manner, the simple ESD network provides sufficient isolation from pin to pin, but does not provide sufficient isolation between the pins and the power supply terminals (positive and negative and/or ground). A potential solution is to use the ESD network with dedicated, quiet supply and/or ground pins.
Many circuits have multiple power inputs with a corresponding multiple of positive and negative supply pins. For example, the IC may include two different circuits, each with a corresponding power input, where each power input has a voltage pin and a ground or negative pin. The internal supply and ground buses may be noisy, so the use of a pair of dedicated ESD rings is commonly used. The dual ring ESD network is similar to the simple ESD network described above, except that the ESD diodes are connected between an ESD high bus line and an ESD low bus line (the buses forming the ESD rings). Also, the positive and negative power pins for the two circuits are coupled to the ESD high and low buses, respectively, in a similar manner. At least one voltage clamp is typically placed between the ESD high and low bus lines. Multiple voltage clamps may be used and placed in parallel at different locations in the IC to reduce the distance traveled by large ESD event currents. For example, two separate voltage clamps may be provided, one for each of the circuits, or four clamps may be distributed among the four corners of the IC, etc.
If the first and second power supply voltages are kept below the breakdown voltage of the clamp devices, the ESD high and low buses are ideally direct current (DC) open-circuited. AC currents and voltages can be coupled through the capacitances of the various ESD diodes and drive the ESD high and low buses. In practice, even for the DC case, diodes are not perfect DC open circuits and some leakage current is often present which causes the ESD high bus to be near one of the positive supply voltages and the ESD low bus to be near ground or a negative supply voltage. The conduction of ESD pulses is similar to that described for the simple ESD circuit described previously when the IC is not connected or not powered. The dual ESD ring configuration provides better isolation between any one or more of the signal pins and the corresponding power supplies, but provides relatively poor isolation between any two or more signal pins.
Radio frequency (RF) ICs, for example, often have multiple circuits and corresponding power inputs, such as separate power inputs for transmit and receive circuitry. For example, a half duplex RF communication system includes a radio that switches between transmit and receive modes of operation. RF ICs require a relatively high pin-to-pin isolation such as equal to or greater than 60 decibel (dB) isolation. The solutions previously described either do not provide the desired level of isolation between the pins or do not provide a practical solution. The dual ring configuration described above does not provide the desired isolation between pins. Additional dedicated supply pins used exclusively for the ESD high and low buses increase package size and cost and are not practical for many RF applications. For example, many RF applications are implemented on battery-powered portable and/or mobile units that require reduced cost, size, power usage and weight solutions and maximal operating efficiency. Larger packages have increased parasitics, which can decrease isolation and overall IC performance. Also, extra pins require additional external components, such as decoupling capacitors and the like, which significantly increases circuit layout area.
SUMMARY OF THE INVENTION
An electrostatic discharge (ESD) switch circuit for an integrated circuit (IC) with multiple power inputs according to the present invention improves pin-to-power isolation of the IC. The IC includes a plurality of positive power pins and a corresponding plurality of negative power pins (which may be ground pins, depending upon the configuration). The IC also includes an ESD ring network with a high ESD bus and a low ESD bus. The IC further includes a control circuit indicating one of several operational modes. The ESD switch circuit includes a first switch circuit that couples the high ESD bus to a first positive power pin in a first operational mode. The ESD switch circuit further includes a second switch circuit that couples the low ESD bus to a first negative power pin in the first operational mode. In this manner, the first and second switch circuits provide greater isolation in the first operational mode.
The first and second switch circuits may further disconnect the high and low ESD buses from the first positive and negative power pins, respectively, in a second operational mode. Such is advantageous, for example, when the first positive and negative power pins are employed to provide power during the second operational mode. The first and second switch circuits may further couple the high and low ESD buses, respectively, to the second positive and negative power pins, respectively, in the second operational mode. In the second operational mode, the first and second switch circuits may further disconnect the high and low ESD buses, respectively, from the second positive and negative power pins, respectively.
The first and second switch circuits may further disconnect the high ESD bus from the first and second positive power pins and the low ESD bus from the first and second negative power pins, respectively, when power is removed. In this manner, when the IC is powered down or otherwise disconnected
Intersil America's Inc.
Nguyen Danny
Sircus Brian
Stanford Gary R.
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