Switched deskew on arbitrary data

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Details

C375S358000, C375S360000, C375S370000, C375S376000, C327S155000, C327S156000, C327S151000, C327S158000

Reexamination Certificate

active

10892760

ABSTRACT:
A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

REFERENCES:
patent: 6292116 (2001-09-01), Wang et al.
patent: 6903575 (2005-06-01), Davidson et al.
patent: 7164742 (2007-01-01), McLeod
Taylor, Ricky et al. 2003. National Semiconductor Advanced Information Spec. Preliminary 1.0. “High-Speed LVDS Receiver FPD00104 Product Development Specification.” Revised Jun. 2, 2003. 28 pages.

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