Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Utility Patent
1999-06-22
2001-01-02
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S153000
Utility Patent
active
06169509
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switched capacitor filter and more particularly, to a switched capacitor filter having an offset canceling function. The present invention also relates to a display driver having the switched capacitor filter.
2. Description of the Prior Art
A liquid crystal display with thin film transistors (TFT) arranged in a matrix (TFT-LCD) is currently required to achieve a high definition, wide visual field and multi-gradation for use in a monitor.
A liquid crystal display driver for supplying a voltage to drive a liquid crystal such as the TFT-LCD is required accordingly to realize a high precision output voltage, a voltage range of 10-20 V and an output duration of about 12-15 &mgr;s.
As shown in
FIG. 1
, a conventional switched capacitor type D/A converter with a function for canceling an offset voltage in operational amplifier A
1
is employed in the display driver so as to realize the high precision output voltage. The switched capacitor type D/A converters as many as, for example, the number of pixels in one line are arranged on an upper side of the display. This prior art includes level voltages V
1
, V
2
and reference voltage Vr as analog inputs, and comprises input capacitors C
0
-Cn with a ratio corresponding to the bit number of input digital data and output capacitor Cc connected to the output. It also includes operational amplifier A
1
using a line connected to the input capacitors and output capacitor in parallel as the inverting input and using a line from reference voltage Vr as the non-inverting input. It further includes switches S
1
-Sn for changing connections between the level voltages and the input capacitors in accordance with the input digital data, and switches SW
1
-SW
5
for changing the operation of the switched capacitor type D/A converter. It still further includes controller for controlling switches SW
1
-
5
. In case of n-bit digital data input, input capacitors C
0
-Cn have capacities of C
0
=Cu, C
1
=Cu, C
2
=2×Cu, C
3
=2×2×Cu, . . . , and Cn (n≧1) has a capacity represented with the product of the (n−1)th power of 2 and Cu where Cu denotes a unit capacity. Magnitudes of level voltages V
1
and V
2
are two of conditions defining a range of voltages that can be output from the switched capacitor type D/A converter of FIG.
1
. The capacity of output capacitor Cc is determined along with level voltages V
1
and V
2
(V
1
>V
2
) so that a ratio between a total sum of the input capacities and the output capacity can realize a desired output variation range of the switched capacitor type D/A converter. A capacity of the output capacitor is represented with Cc=(x×Cu) using unit capacity Cu. Reference voltage Vr is amplified and output in accordance with an amplification degree that is determined on the basis of a capacity ratio between output capacity Cc and the total sum of the input capacities C
0
-Cn, and accordingly, is a voltage to determine a reference for the output voltage.
Operations of the conventional switched capacitor type D/A converter with offset canceling function will be explained below with reference to FIG.
2
. Switches SW
1
and Sn in
FIG. 1
are turned to H when levels of respective signals in
FIG. 2
becomes high, while they are turned to L when levels of respective signals in
FIG. 2
becomes low. Switches SW
2
to SW
5
are turned on when levels of respective signals in
FIG. 2
becomes high, while they are turned of f when levels of respective signals in
FIG. 2
becomes low.
In initial state (or output mode), SW
1
is set to L, SW
3
and SW
5
are set to OFF, SW
2
and SW
4
are set to ON, and S
1
through Sn are set to either of H state or L state in accordance with input digital data. As described later, output voltage Vo is represented by:
Vo
=(1+(
n′/x
))×
Vr
−(
n′/x
)×(
V
2
+(/
n
′)×(
V
1
−
V
2
)) (1),
where n′ denotes the n-th power of 2, and is an amount corresponding to n-bit input data, which exhibits numerals of 1 to (n′−1).
In reset mode subsequent to output mode, SW
1
is set to H, SW
3
and SW
5
are set to ON, SW
2
and SW
4
are set to OFF, and S
1
-Sn are set to L. The switched capacitor type D/A converter in this mode functions as a voltage follower and a voltage of Vr+&Dgr;Vos (&Dgr;Vos is an offset voltage of amplifier A
1
) appears at point a in the circuit. Therefore, the voltage, Vr+&Dgr;Vos, is applied to terminals of input capacitors C
0
-Cn and output capacitor Cc, at a side to which point a is connected. Vr is also applied to another terminals of input capacitors C
0
-Cn and output capacitor Cc.
Therefore, the following charges are accumulated in input capacitors C
0
-Cn and output capacitor Cc:
(
Vr+&Dgr;Vos−Vr
)×
C
0
+ . . . +(
Vr+&Dgr;Vos−Vr
)×
Cn
+(
Vr+&Dgr;Vos−Vr
)×
Cc=&Dgr;Vos
×(
n′+x
)×
Cu
(2)
In output mode subsequent to reset mode, SW
1
is set to L, SW
3
and SW
5
are set to OFF, SW
2
and SW
4
are set to ON, and S
1
-Sn are set to H or L in accordance with the input digital data.
In this output mode, the following charges are accumulated in input capacitors C
0
-Cn and output capacitor Cc:
(
Va−V
1
)× ×
Cu
+(
Va−V
2
)×(
n
′−)×
Cu
+(
Va−Vo
)×
Cc
(3),
where Va denotes a voltage at point a. As a voltage of Vr is applied to the non-inverting input of operational amplifier A
1
, Va=Vr+&Dgr;Vos results. Right-hand side of Equations (2) and Equation (3) are equal because the charges in the reset and output modes are reserved. Equation (1) is derived by solving the equation relating equations (2) and (3) with respect to Vo while substituting Va=Vr+&Dgr;Vos.
The switched capacitor type D/A converter with offset canceling function, which is not affected by the offset voltage, &Dgr;Vos, of operational amplifier A
1
, can be configured with the above operation.
The above prior art is a circuit which satisfies a request for the high precision output among requests to a source driver for TFT-LCD. There is desired a circuit which further satisfies a request for achieving the output voltage range of 10-20 V and a request for realizing the output duration of about 12-15 &mgr;s simultaneously.
However, in the prior art, when the request for realizing the output voltage range of 10-20 V is satisfied, there is a large difference between output voltage (Vr+&Dgr;Vos) which is output from the circuit functioning as a voltage follower at the final stage in the reset mode and output voltage Vo, which is the last voltage in the last output mode, at the first stage in the reset mode. Therefore, a duration of at least ((Vo−(Vr+&Dgr;Vos))/&bgr;)(&mgr;/s) is necessary until the output voltage at (Vr+&Dgr;Vos) is stabilized after entering into the reset mode if a slew rate of operational amplifier A
1
is &bgr;(V/&mgr;s).
FIG. 3
shows time variations of the voltages at points a and k in the conventional circuit of FIG.
1
. The duration for stabilizing the voltage follower output is referred to as a reset duration and is necessary one inserted between the output modes. If the reset duration becomes long, it is reduced an output duration for actually applying a voltage to TFT-LCD, resulting in a disadvantage that the high precision voltage can not be applied on TFT-LCD.
In the prior art, in order to solve the above disadvantage, the reset duration is shortened by increasing a current flowing in the operational amplifier only in the reset duration and thereby increasing the slew rate of the operational amplifier in the reset duration. According to such approach, a reset duration of 2-3 &mgr;s can be realized currently. The above approach, however, includes the following disadvantages:
a current consumption increases;
the oper
McGinn & Gibb, P.C.
NEC Corporation
Tokar Michael
Tran A.
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