Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating
Reexamination Certificate
2000-07-21
2003-05-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
By integrating
C327S540000, C327S576000
Reexamination Certificate
active
06566933
ABSTRACT:
FIELD
This invention relates generally to a high-speed differential current switches. More specifically, this invention relates to pre-driver techniques for high-speed differential current switches.
BACKGROUND OF THE INVENTION
In conventional data communication systems, integrated circuit designs often depend on having a high-speed differential current switch. Differential signals are used in specialized versions of SCSI, in twisted-pair local area networks, and other high-speed applications. The most common differential switch is the differential pair
10
shown in FIG.
1
.
The prior art as depicted in
FIG. 1
shows two Metal Oxide Semiconductor (MOS) devices
12
and
14
with their sources connected together (a differential pair), together with a current source
16
supplying current
10
to the common source node of the differential pair. When the gate
20
of MOS
12
is driven to a high voltage and the gate
22
of MOS
14
is driven to a low voltage (V
1
>V
2
), any circuitry at the drain
24
of MOS
12
will see I
1
=I
0
, while any circuitry at the drain
28
of MOS
14
will see I
2
=0. If the gate voltages of M
1
and M
2
are reversed (V
2
>V
1
), such that the gate
20
of MOS
12
is driven to a low voltage and the gate
22
of MOS
14
is driven to a high voltage, then at drain
24
, I
1
=0 and at drain
28
, I
2
=I
0
.
The gate voltages V
1
and V
2
of MOS
12
and MOS
14
can be driven high and low under control of digital circuitry. This provides high-speed current switching for application in high-speed line drivers, current-mode D/A converters, and PLL charge pumps among others.
The simplest way to drive the gates
20
and
22
of MOS
12
and MOS
14
, respectively, is to simply apply complementary rail-to-rail digital signals to them. This system works sufficiently well for a number of low-speed applications but is impractical for more demanding high-speed applications.
Furthermore, this system is susceptible to distortion in the output waveforms I
1
and I
2
. This distortion may result from charge injection across the gate-drain overlap capacitances of MOS
12
and MOS
14
, channel charge injection from MOS
12
and MOS
14
, and voltage transients on the common drain node. Any voltage transient on the common source node of MOS
12
and MOS
14
results in common-mode currents in I
1
and I
2
from parasitic capacitance charging and discharging. Voltage transients on this node also modulate the output current of I
0
.
Traditionally, there are two techniques that can be readily applied, either singly, or in combination, that may significantly reduce the distortion described above. The first is to apply gate voltages to MOS
12
and MOS
14
such that MOS
12
is turned on before MOS
14
is shut off (and vice-versa),
The second technique is to minimize the difference between voltages applied to MOS
12
and MOS
14
using a pre-driver. This minimizes gate/drain overlap charge injection and voltage transients on the common source node, thereby minimizing the common-mode current transients. In general, there are four methods by which the second technique may be carried out. Four pre-driver circuits showing four separate methods to generate reduced-swing gate voltages for MOS
12
and MOS
14
are shown in
FIGS. 2
a
to
2
d.
Referring to
FIG. 2
a
, the first method uses resistive dividers
32
and
34
on the outputs of two standard CMOS inverters
36
and
38
, respectively, to produce two voltages V
1
and V
2
between the rails. The resistors of the resistive dividers
32
and
34
are generally approximated using MOS transistors, and as a result the output voltages V
1
and V
2
are usually poorly controlled over process variations, temperature, and power supply voltage.
Referring to
FIG. 2
b
, the second method uses a second differential pair
40
and
42
driven into a cross-coupled latch
44
to produce the two gate voltages V
1
and V
2
. Similar to the first method, the voltages V
1
and V
2
are determined by the characteristics of MOS transistors, and are usually poorly controlled.
Referring to
FIG. 2
c
, the third method is similar to the second, using a differential pair
46
and
48
but replacing the cross-coupled latch with resistors
50
and
52
. As resistors have replaced the MOS transistors of the second method, the resistor, current source and gate voltages can potentially be well controlled. However, the use of resistors consumes a relatively large quantity of power.
Referring to
FIG. 2
d
, the fourth method uses amplifiers
54
and
56
to buffer separately generated reference voltages VREF
1
and VREF
2
, then using a switching matrix
58
to connect the buffered voltages V
1
and V
2
to the gates of MOS
12
and MOS
14
.
The first three methods (see
FIGS. 2
a
,
2
b
and
2
c
) all suffer from high power consumption. This is a result of having to drive the gate capacitances of MOS
12
and MOS
14
: as the current I
0
becomes larger, MOS
12
and MOS
14
become wider, and the gate capacitances of MOS
12
and MOS
14
become larger. As a result, the effective output resistance from resistive dividers
32
and
34
, resistors
50
and
52
and the cross-coupled latch
44
must be reduced in order to keep the signal slew rate high and therefore the circuit speed high. The output voltages V
1
and V
2
are generated by driving a current through the output resistance (resistive dividers
32
and
34
, resistors
50
and
52
and the cross-coupled latch
44
), thus, the standing current in the system rises and therefore so does the power dissipation.
Similarly, if the frequency of switching increases while the dimensions of MOS
12
and MOS
14
are kept constant, the time constant of the pre-driver output must go down, therefore its output resistance must go down, again requiring an increase in standing current. As a result, the power dissipated in the pre-driver is roughly proportional both to I
0
and to the switching frequency.
The fourth method also requires large standing currents, but for different reasons than described for the first three methods. By separately generating the voltages VREF
1
and VREF
2
and then buffering them on two holding capacitors, the amplifiers
54
and
56
only have to provide current to replenish charge drawn from the capacitors during switching.
The major shortcoming of the fourth method is that the required current out of the amplifiers
54
and
56
when transmitting data is data transition density dependent. Therefore, during periods of high transition density, on average more charge will be pulled from the holding capacitors than during low transition density periods. To avoid introducing data-dependent jitter on the outputs V
1
and V
2
, the amplifiers
54
and
56
need to replenish the charge within one sample time. As a result, the required amplifier bandwidth is quite large, which usually requires a single-stage amplifier structure with a lot of standing current. To reduce the standing current, a lower-power 2-stage amplifier may be used, but this approach is not preferred due to the difficulty in compensating that amplifier and still getting the required bandwidth. An alternate approach is to reduce the size of the holding capacitors, this will make the 2-stage amplifier compensation easier, but will result in unwanted transient signals on the buffer outputs. A further alternate approach is to add a low-impedance stage to the 2-stage amplifiers' output that would reduce the transient effects, but will also add standing current. Therefore, the fourth method (
FIG. 2
d
) results in standing currents comparable to the first three methods (
FIGS. 2
a
-
2
c
), with similar power dissipation.
Clearly, as the speed of a transmitter goes higher, the power penalty of constructing a high-current off-chip transmitter pre-driver using these techniques becomes prohibitive.
It is, therefore, an object of this invention to provide an improved transmitter pre-driver that minimizes power dissipation.
It is a further object of this invention to provi
Callahan Timothy P.
Hall Priddy Myers & Vande Sande
Nguyen Hai L.
PMC-Sierra Inc.
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