Switched capacitor offset suppression

Amplifiers – With periodic switching input-output

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330 51, H03F 114

Patent

active

057397201

ABSTRACT:
A switched-capacitor circuit that includes a first signal path disposed between a first input node and a first output node, and a second signal path disposed between a second input node and a second output node. The first and second switches can be alternately disposed within the first and second signal paths. An amplifier responsive to the switches can be provided, and its offset can be cancelled. The outputs of the amplifiers can be maintained, and this can involve buffering.

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D.B. Ribner, R.D. Baertsch, S.L. Garverick, D.T. McGrath, J.E. Krisciunas, and T.Fuji, "A Third-Order Multistage Sigma-Delta Modulator With Reduced Sensitivity to Nonidealities," IEEE Journal of Solid-State Circuits, vol. 26, No. 12, pp. 1764-1773, Dec. 1991.
K. Nagarai, K. Singhal, T.R. Viswanathan, and J. Vlach, J.; "Reduction of Finite-gain Effect in Switched-capacitor Filters," Electronics Letters, vol. 21, No. 15, pp. 644-645, Jul. 18th, 1985.
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